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| Preliminary Technical Data FEATURES 8 channels of LNA, VGA, AAF, and ADC Low noise preamplifier (LNA) Input-referred noise = 1.2 nV/Hz @ 7.5 MHz typical SPI-programmable gain = 14 dB/15.6 dB/18 dB Single-ended input; VIN maximum = 400 mV p-p/ 333 mV p-p/250 mV p-p Dual mode, active input impedance match Bandwidth (BW) > 70 MHz Full-scale (FS) output = 2 V p-p diff Variable gain amplifier (VGA) Gain range = -6 dB to +24 dB Linear-in-dB gain control Antialiasing filter (AAF) 3rd-order Butterworth cutoff Programmable from 8 MHz to 18 MHz Analog-to-digital converter (ADC) 12 bits at 10 MSPS to 50 MSPS SNR = 70 dB SFDR = 80 dB Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link) Data and frame clock outputs Includes crosspoint switch to support continuous wave (CW) Doppler Low power, 150 mW/channel at 12 bits/40 MSPS (TGC) 60 mW/channel in CW Doppler Single 1.8 V supply (3.3 V supply for CW Doppler output bias) Flexible power-down modes Overload recovery in <10 ns Fast recovery from low power standby mode, <2 s 100-pin TQFP Octal LNA/VGA/AAF/ADC and Crosspoint Switch AD9271 The LNA has a single-ended-to-differential gain that is selectable through the SPI. The LNA input noise is typically 1.2 nV/Hz, FUNCTIONAL BLOCK DIAGRAM DRVDD PWDN STDBY AVDD LOSW-A LO-A LI-A LG-A LOSW-B LO-B LI-B LG-B LOSW-C LO-C LI-C LG-C LOSW-D LO-D LI-D LG-D LOSW-E LO-E LI-E LG-E LOSW-F LO-F LI-F LG-F LOSW-G LO-G LI-G LG-G LO-H LOSW-H LI-H LG-H VGA AAF AD9271 LNA VGA AAF 12-BIT PIPELINE ADC SERIAL LVDS DOUT + A DOUT - A LNA VGA AAF 12-BIT PIPELINE ADC SERIAL LVDS DOUT + B DOUT - B LNA VGA AAF 12-BIT PIPELINE ADC SERIAL LVDS DOUT + C DOUT - C LNA 12-BIT PIPELINE ADC SERIAL LVDS DOUT + D DOUT - D LNA VGA AAF 12-BIT PIPELINE ADC SERIAL LVDS DOUT + E DOUT - E LNA VGA AAF 12-BIT PIPELINE ADC SERIAL LVDS DOUT + F DOUT - F LNA VGA AAF 12-BIT PIPELINE ADC SERIAL LVDS DOUT + G DOUT - G APPLICATIONS Medical imaging/ultrasound Automotive radar LNA VGA AAF 12-BIT PIPELINE ADC SERIAL LVDS DOUT + H DOUT - H SERIAL PORT INTERFACE gm 6 SWITCH ARRAY REFERENCE DATA RATE MULTIPLIER FCO+ FCO- DCO+ DCO- GENERAL DESCRIPTION The AD9271 is designed for low cost, low power, small size, and ease of use. It contains eight channels of a variable gain amplifier (VGA) with low noise preamplifier (LNA); an antialiasing filter (AAF); and a 12-bit, 10 MSPS to 50 MSPS analog-to-digital converter (ADC). Each channel features a variable gain range of 30 dB, a fully differential signal path, an active input preamplifier termination, a maximum gain of up to 40 dB, and an ADC with a conversion rate of up to 50 MSPS. The channel is optimized for dynamic performance and low power in applications where a small package size is critical. SENSE VREF REFB REFT RBIAS GAIN- CWVDD CWD+/-[5:0] GAIN+ CLK + CLK - CSB SCLK SDIO Figure 1.Block Diagram and the combined input-referred noise of the entire channel is 1.4 nV/Hz at maximum gain. Assuming a 15 MHz noise bandwidth (NBW) and a 15.6 dB LNA gain, the input SNR is roughly 86 dB. In CW Doppler mode, the LNA output drives a transconductance amp that is switched through an 8 x 6, differential crosspoint switch. The switch is programmable through the SPI. Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved. 06304-001 AD9271 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Product Highlights ........................................................................... 3 Specifications..................................................................................... 4 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 8 Switching Specifications .............................................................. 9 ADC Timing Diagrams ................................................................. 10 Absolute Maximum Ratings.......................................................... 11 Thermal Impedance ................................................................... 11 ESD Caution................................................................................ 11 Pin Configuration and Function Descriptions........................... 12 Equivalent Circuits ......................................................................... 15 Typical Performance Characteristics ........................................... 17 Theory of Operation ...................................................................... 20 Ultrasound................................................................................... 20 Channel Overview...................................................................... 21 Preliminary Technical Data Input Overdrive .......................................................................... 23 CW Doppler Operation............................................................. 23 TGC Operation........................................................................... 25 A/D Converter ............................................................................ 28 Clock Input Considerations...................................................... 28 Serial Port Interface (SPI).............................................................. 35 Hardware Interface..................................................................... 35 Memory Map .................................................................................. 37 Reading the Memory Map Table.............................................. 37 Reserved Locations .................................................................... 37 Default Values ............................................................................. 37 Logic Levels................................................................................. 37 Evaluation Board ............................................................................ 42 Power Supplies ............................................................................ 42 Input Signals................................................................................ 42 Output Signals ............................................................................ 42 Default Operation and Jumper Selection Settings................. 43 Outline Dimensions ....................................................................... 56 Ordering Guide .......................................................................... 56 REVISION HISTORY x/07--Revision 0: Initial Version Rev. PrA | Page 2 of 58 Preliminary Technical Data The AD9271 requires a LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO) for capturing data on the output and a frame clock (FCO) trigger for signaling a new output byte are provided. Powering down individual channel is supported to increase battery life for portable applications. There is also a standby mode option that allows quick power-up for power cycling. In CW Doppler operation, the VGA, AAF, and ADC are powered down. The power of the TGC path scales with selectable speed grades. The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudorandom pattern, and custom user-defined test patterns entered via the serial port interface. AD9271 Fabricated in an advanced CMOS process, the AD9271 is available in a 14 mm x 14 mm, Pb-free, 100-lead TQFP. It is specified over the industrial temperature range of -40C to +85C. PRODUCT HIGHLIGHTS 1. Small Footprint. Eight channels are contained in a small, space-saving package. Full TGC path, ADC, and crosspoint switch contained within a 100-lead, 16 mm x 16 mm, TQFP. Low power of 150 mW/channel at 40 MSPS. Integrated Crosspoint Switch. This switch allows numerous multichannel configuration options to enable the CW Doppler mode. Ease of Use. A data clock output (DCO) operates up to 300 MHz and supports double data rate operation (DDR). User Flexibility. Serial port interface (SPI) control offers a wide range of flexible features to meet specific system requirements. Integrated Third-Order Antialiasing Filter. This filter is placed between TGC path and ADC and is programmable from 8 MHz to 18 MHz. 2. 3. 4. 5. 6. Rev. PrA | Page 3 of 58 AD9271 SPECIFICATIONS AC SPECIFICATIONS Preliminary Technical Data AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 1.0 V internal ADC reference, AIN = 5 MHz, RS = 50 , LNA gain = 15.6 dB (6), unless otherwise noted. Table 1. Parameter1 LNA CHARACTERISTICS Gain = 5/6/8 Conditions Min AD9271-25 Typ Max Min AD9271-40 Typ Max Min AD9271-50 Typ Max Unit Input Voltage Range, Gain = 5/6/8 Single-ended input to differential output Single-ended input to single-ended output LNA output limited to 2 V p-p differential output 14/15.6/18 14/15.6/18 14/15.6/18 dB 8/9.6/12 8/9.6/12 8/9.6/12 dB 400/333/250 400/333/250 400/333/250 mV p-p SE2 Input Common Mode Input Resistance 1.4 RFB = 200 , RFB = 400 , RFB = LI-x RS = 0 , RFB = VGAIN = 0 V 50 100 15 15 40 1.4/1.4/1.3 1.4 50 100 15 15 60 1.3/1.2/1.1 1.4 50 100 15 15 70 1.3/1.2/1.1 V k pF MHz nV/Hz Input Capacitance -3 dB Bandwidth Input Noise Voltage, Gain = 5/6/8 1 dB Input Compression Point Gain = 5/6/8 Active Termination Match Unterminated FULL-CHANNEL (TGC) CHARACTERISTICS AAF High-Pass Cutoff AAF Low-Pass Cutoff Group Delay Variation Bandwidth Tolerance Input-Referred Noise Voltage, LNA Gain = 5/6/8 Correlated Noise Output Offset Signal-to-Noise Ratio (SNR) FIN = 5 MHz at -7 dBFS 782.6/649.1/508.8 782.6/649.1/508.8 782.6/649.1/508.8 mV p-p , RFB = 200 6.7 6.7 6.7 dB RFB = 4.9 4.4 4.2 dB -3 dB -3 dB, programmable f = 1 MHz to 10 MHz, gain = 0 V to 1 V DC/350/700 1/3 x fSAMPLE (8 to 18) 1 DC/350/700 1/3 x fSAMPLE (8 to 18) 1 DC/350/700 1/3 x fSAMPLE (8 to 18) 1 kHz MHz ns 15 RFB = 1.7/1.6/1.5 15 1.6/1.4/1.3 15 1.6/1.4/1.2 % nV/Hz No signal AAF high-pass = 700 kHz -30 TBD -30 TBD -30 TBD dB LSB GAIN pin = 0 V 65 65 65 dBFS Rev. PrA | Page 4 of 58 Preliminary Technical Data Parameter1 FIN = 5 MHz at -1 dBFS Harmonic Distortion Second Harmonic, FIN = 5 MHz at -7 dBFS Second Harmonic, FIN = 5 MHz at -1 dBFS Third Harmonic, FIN = 5 MHz at -7 dBFS Third Harmonic, FIN = 5 MHz at -1 dBFS Two-Tone IMD3 (2 x F1 - F2) Distortion FIN1 = 5.0 MHz at -1 dBFS FIN2 = 5.1 MHz at -26 dBFS Channel-toChannel Crosstalk Channel-toChannel Crosstalk (Overrange Condition)3 Overload Recovery GAIN ACCURACY Absolute Gain Error Conditions GAIN pin = 1 V Min AD9271-25 Typ 65 Max Min AD9271-40 Typ 65 Max Min AD9271-50 Typ 65 AD9271 Max Unit dBFS GAIN pin = 0 V -65 -65 -65 dBFS GAIN pin = 1 V -65 -65 -65 dBFS GAIN pin = 0 V -70 -70 -70 dBFS GAIN pin = 1 V -70 -70 -70 dBFS GAIN pin = 1 V -65 -65 -65 dB -70 -70 -70 dB -70 -70 -70 dB LNA or VGA 0 < VGAIN < 0.1 V 0.1 V < VGAIN < 0.9 V, 1 0.9 V < VGAIN < 1V 0.1 V < VGAIN < 0.9 V -1.0 -1.0 -2.0 10 +0.5 +0.3 -0.5 +2.0 +1.0 +1.0 1 -1.0 -1.0 -2.0 10 +0.5 +0.3 -0.5 +2.0 +1.0 +1.0 1 -1.0 -1.0 -2.0 10 +0.5 +0.3 -0.5 +2.0 +1.0 +1.0 1 ns dB dB dB dB Channel-toChannel Matching GAIN CONTROL INTERFACE Normal Operating Range Gain Range Scale Factor Response Time CW DOPPLER MODE Transconductance, LNA Gain = 5/6/8 Common Mode Input-Referred Noise Voltage, LNA Gain = 5/6/8 Output DC Bias Maximum Output Swing POWER SUPPLY AVDD 0 0 V to 1 V 30 dB change 10.6 32 350 10/12/16 1 40.6 0 10.6 32 350 10/12/16 1 40.6 0 10.6 32 350 10/12/16 1 40.6 V dB dB/V ns mA/V CW Doppler output pins RS = 0 , RFB = 1.5 1.8 /1.7/1.5 3.6 1.5 1.7 /1.5/1.4 3.6 1.5 1.7 /1.5/1.3 3.6 V nV/Hz Per channel Per channel 2.4 2 2.4 2 2.4 2 mA mA pp 1.9 V 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 Rev. PrA | Page 5 of 58 AD9271 Parameter1 DRVDD CWVDD IAVDD Conditions Min 1.7 3.0 AD9271-25 Typ 1.8 3.3 500 136 Max 1.9 3.6 Min 1.7 3.0 AD9271-40 Typ 1.8 3.3 622 160 Preliminary Technical Data Max 1.9 3.6 Min 1.7 3.0 AD9271-50 Typ 1.8 3.3 746 170 Max 1.9 3.6 Unit V mA mA Full-channel mode CW Doppler mode with four channels enabled Full-channel mode IDRVDD Total Power Dissipation (Including Output Drivers) 49 984 49 1200 49 1400 mA mW CW Doppler mode with four channels enabled Power-Down Dissipation Standby Power Dissipation Power Supply Rejection Ratio (PSRR) ADC RESOLUTION 192 216 224 mW 10 65 1 65 1 65 1 mW mW mV/V 12 12 12 Bits Rev. PrA | Page 6 of 58 Preliminary Technical Data Parameter1 ADC REFERENCE Output Voltage Error (VREF = 1 V) Load Regulation @ 1.0 mA (VREF = 1 V) Input Resistance 1 2 AD9271 AD9271-25 Typ 2 Max Min AD9271-40 Typ 2 Max Min AD9271-50 Typ 2 Max Unit mV Conditions Min 3 3 3 mV 6 6 6 k See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. SE = single ended. 3 The overrange condition is specified as being 6 dB more than the full-scale input range. Rev. PrA | Page 7 of 58 AD9271 DIGITAL SPECIFICATIONS Preliminary Technical Data AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 400 m V p-p differential input, 1.0 V internal ADC reference, AIN = -0.5 dBFS, unless otherwise noted. Table 2. Parameter1 CLOCK INPUTS (CLK+, CLK-) Logic Compliance Differential Input Voltage2 Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, STBY, SCLK) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (CSB) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (SDIO) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO)3 Logic 1 Voltage (IOH = 800 A) Logic 0 Voltage (IOL = 50 A) DIGITAL OUTPUTS (D+, D-), (ANSI-644)1 Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) DIGITAL OUTPUTS (D+, D-), (Low Power, Reduced Signal Option)1 Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) 1 2 Temperature Min Typ Max Unit CMOS/LVDS/LVPECL Full Full 25C 25C Full Full 25C 25C Full Full 25C 25C Full Full 25C 25C Full Full 250 1.2 20 1.5 1.2 30 0.5 1.2 70 0.5 1.2 0 30 2 1.79 0.05 LVDS Full Full 247 1.125 Offset binary 454 1.375 mV V DRVDD + 0.3 0.3 3.6 0.3 3.6 0.3 mV p-p V k pF V V k pF V V k pF V V k pF V V LVDS Full Full 150 1.10 Offset binary 250 1.30 mV V See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Specified for LVDS and LVPECL only. 3 Specified for 13 SDIO pins sharing the same connection. Rev. PrA | Page 8 of 58 Preliminary Technical Data SWITCHING SPECIFICATIONS AD9271 AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 400 m V p-p differential input, 1.0 V internal ADC reference, AIN = -0.5 dBFS, unless otherwise noted. Table 3. Parameter1 CLOCK2 Maximum Clock Rate Minimum Clock Rate Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) OUTPUT PARAMETERS2, 3 Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) FCO Propagation Delay (tFCO) DCO Propagation Delay (tCPD)4 DCO to Data Delay (tDATA)4 DCO to FCO Delay (tFRAME)4 Data-to-Data Skew (tDATA-MAX - tDATA-MIN) Wake-Up Time (Standby) Wake-Up Time (Power-Down) Pipeline Latency APERTURE Aperture Uncertainty (Jitter) 1 2 Temp Full Full Full Full Full Full Full Full Full Full Full Full 25C 25C Full Min 50 Typ Max Unit MSPS MSPS ns ns ns ps ps ns ns ps ps ps ns s CLK cycles ps rms 10 10.0 10.0 1.5 2.3 300 300 1.5 2.3 3.1 3.1 (tSAMPLE/24) - 300 (tSAMPLE/24) - 300 tFCO + (tSAMPLE/24) (tSAMPLE/24) (tSAMPLE/24) 50 600 375 8 (tSAMPLE/24) + 300 (tSAMPLE/24) + 300 200 25C <1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Can be adjusted via the SPI interface. 3 Measurements were made using a part soldered to FR4 material. 4 tSAMPLE/24 is based on the number of bits divided by 2, because the delays are based on half duty cycles. Rev. PrA | Page 9 of 58 AD9271 ADC TIMING DIAGRAMS N-1 AIN Preliminary Technical Data tA N CLK- tEH tEL CLK+ tCPD DCO- DCO+ tFCO FCO- tFRAME FCO+ tPD DOUT- MSB N-8 D10 N-8 D9 N-8 D8 N-8 D7 N-8 tDATA D6 N-8 D5 N-8 D4 N-8 D3 N-8 D2 N-8 D1 N-8 D0 N-8 MSB N-7 D10 N-7 DOUT+ Figure 2. 12-(Preliminary) Bit Data Serial Stream (Default) N-1 AIN tA N tEH CLK- tEL CLK+ tCPD DCO- DCO+ tFCO FCO- tFRAME FCO+ tPD DOUT- LSB (N - 8) DOUT+ D0 (N - 8) D1 (N - 8) D2 (N - 8) tDATA D3 D4 (N - 8) (N - 8) D5 (N - 8) D6 (N - 8) D7 (N - 8) D8 (N - 8) D9 (N - 8) D10 (N - 8) LSB (N - 7) D0 (N - 7) 06304-004 Figure 3. 12-(Preliminary) Bit Data Serial Stream, LSB First Rev. PrA | Page 10 of 58 06304-002 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 4. Parameter ELECTRICAL AVDD DRVDD CWVDD GND AVDD Digital Outputs (DOUT+, DOUT-, DCO+, DCO-, FCO+, FCO-) CLK+, CLK- LI-x LO-x LOSW-x CWDx-, CWDx+ SDIO, GAIN+,GAIN- PDWN, STBY, SCLK, CSB REFT, REFB, RBIAS VREF, SENSE ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) With Respect To GND GND GND GND DRVDD GND Rating -0.3 V to +2.0 V -0.3 V to +2.0 V -0.3 V to +3.9 V -0.3 V to +0.3 V -2.0 V to +2.0 V -0.3 V to +2.0 V AD9271 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL IMPEDANCE Table 5. Air Flow Velocity (m/s) 0.0 1.0 2.5 1 GND LG-x LG-x LG-x GND GND GND GND GND -0.3 V to +3.9 V -0.3 V to +2.0 V -0.3 V to +2.0 V -0.3 V to +2.0 V -0.3 V to +2.0 V -0.3 V to +2.0 V -0.3 V to +3.9 V -0.3 V to +2.0 V -0.3 V to +2.0 V -40C to +85C 150C 300C -65C to +150C JA1 20.3C/W 14.4C/W 12.9C/W JB 7.6C/W JC 4.7C/W JA for a 4-layer PCB with solid ground plane (simulated). Exposed pad soldered to PCB. ESD CAUTION Rev. PrA | Page 11 of 58 AD9271 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 100 LOSW-E 84 CWVD-D Preliminary Technical Data 76 LOSW-D 75 LI-D 74 LG-D 73 AVDD 72 AVDD EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE) 71 LO-C 70 LOSW-C 69 LI-C 68 LG-C 67 AVDD 66 AVDD 65 LO-B 64 LOSW-B 63 LI-B 62 LG-B 61 AVDD 60 AVDD 59 LO-A 58 LOSW-A 57 LI-A 56 LG-A 55 AVDD 54 AVDD 53 CSB 52 SDIO 51 SCLK 98 CWD5+ 96 CWD4+ 94 CWD3+ 83 CWD2+ 81 CWD1+ 79 CWD0+ 97 CWD5- 95 CWD4- 93 CWD3- 82 CWD2- 80 CWD1- 78 CWD0- 88 SENSE 87 RBIAS 86 GAIN+ 85 GAIN- 92 AVDD 90 REFB LI-E 1 LG-E 2 AVDD 3 AVDD 4 LO-F 5 LOSW-F 6 LI-F 7 LG-F 8 AVDD 9 AVDD 10 LO-G 11 LOSW-G 12 LI-G 13 LG-G 14 AVDD 15 AVDD 16 LO-H 17 LOSW-H 18 LI-H 19 LG-H 20 AVDD 21 AVDD 22 CLK- 23 CLK+ 24 AVDD 25 PIN 1 INDICATOR AD9271 TOP VIEW (Not to Scale) DRVDD 26 DOUT - H 27 DOUT + H 28 DOUT - G 29 DOUT + G 30 DOUT - F 31 DOUT + F 32 DOUT - E 33 DOUT + E 34 DCO- 35 DCO+ 36 FCO- 37 FCO+ 38 DOUT - D 39 DOUT + D 40 DOUT - C 41 DOUT + C 42 DOUT - B 43 DOUT + B 44 DOUT - A 45 DOUT + A 46 DRVDD 47 STBY 48 PWDN 49 AVDD 50 77 LO-D 89 VREF 99 LO-E 91 REFT Figure 4. 100-Lead TQFP Table 6. Pin Function Descriptions Pin No. 0 3, 4, 9, 10, 15, 16, 21, 22, 25, 50, 54, 55, 60, 61, 66, 67, 72, 73,92 26, 47 84 1 2 5 6 7 8 11 12 13 14 Name GND AVDD Description Ground (Exposed paddle should be tied to a quiet analog ground) 1.8 V Analog Supply DRVDD CWVDD LI-E LG-E LO-F LOSW-F LI-F LG-F LO-G LOSW-G LI-G LG-G 1.8 V Digital Output Driver Supply 3.3 V Analog Supply LNA Analog Input for Channel E LNA Ground for Channel E LNA Analog Output for Channel F LNA Analog Output Complement for Channel F LNA Analog Input for Channel F LNA Ground for Channel F LNA Analog Output for Channel G LNA Analog Output Complement for Channel G LNA Analog Input for Channel G LNA Ground for Channel G Rev. PrA | Page 12 of 58 06304-005 Preliminary Technical Data Pin No. 17 18 19 20 23 24 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 48 49 51 52 53 56 57 58 59 62 63 64 65 68 69 70 71 74 75 76 77 78 79 80 81 82 83 Name LO-H LOSW-H LI-H LG-H CLK- CLK+ DOUT - H DOUT + H DOUT - G DOUT + G DOUT - F DOUT + F DOUT - E DOUT + E DCO- DCO+ FCO- FCO+ DOUT - D DOUT + D DOUT - C DOUT + C DOUT - B DOUT + B DOUT - A DOUT + A STDBY PDWN SCLK SDIO CSB LG-A LI-A LOSW-A LO-A LG-B LI-B LOSW-B LO-B LG-C LI-C LOSW-C LO-C LG-D LI-D LOSW-D LO-D CWD0- CWD0+ CWD1- CWD1+ CWD2- CWD2+ Description LNA Analog Output for Channel H LNA Analog Output Complement for Channel H LNA Analog Input for Channel H LNA Ground for Channel H Clock Input Complement Clock Input True ADC H Digital Output Complement ADC H True Digital Output True ADC C Digital Output Complement ADC C True Digital Output ADC B Digital Output Complement ADC B True Digital Output True ADC A Digital Output Complement ADC A True Digital Output True Frame Clock Digital Output Complement Frame Clock Digital Output True Frame Clock Digital Output Complement Frame Clock Digital Output True ADC H Digital Output Complement ADC H True Digital Output True ADC C Digital Output Complement ADC C True Digital Output ADC B Digital Output Complement ADC B True Digital Output True ADC A Digital Output Complement ADC A True Digital Output True Standby Power Down Full Power Down Serial Clock Serial Data Input/Output Chip Select Bar LNA Ground for Channel A LNA Analog Input for Channel A LNA Analog Output Complement for Channel A LNA Analog Output for Channel A LNA Ground for Channel B LNA Analog Input for Channel B LNA Analog Output Complement for Channel B LNA Analog Output for Channel B LNA Ground for Channel C LNA Analog Input for Channel C LNA Analog Output Complement for Channel C LNA Analog Output for Channel C LNA Ground for Channel D LNA Analog Input for Channel D LNA Analog Output Complement for Channel D LNA Analog Output for Channel D CW Doppler Output Complement for Channel 0 CW Doppler Output True for Channel 0 CW Doppler Output Complement for Channel 1 CW Doppler Output True for Channel 1 CW Doppler Output Complement for Channel 2 CW Doppler Output True for Channel 2 Rev. PrA | Page 13 of 58 AD9271 AD9271 Pin No. 85 86 87 88 89 90 91 93 93 95 96 97 98 99 100 Name GAIN- GAIN+ RBIAS SENSE VREF REFB REFT CWD3- CWD3+ CWD4- CWD4+ CWD5- CWD5+ LO-E LOSW-E Preliminary Technical Data Description GAIN Control Voltage Input Complement GAIN Control Voltage Input True External resistor sets the internal ADC core bias current Reference Mode Selection Voltage Reference Input/Output Differential Reference (Negative) Differential Reference (Positive) CW Doppler Output Complement for Channel 3 CW Doppler Output True for Channel 3 CW Doppler Output Complement for Channel 4 CW Doppler Output True for Channel 4 CW Doppler Output Complement for Channel 5 CW Doppler Output True for Channel 5 LNA Analog Output for Channel E LNA Analog Output Complement for Channel E Rev. PrA | Page 14 of 58 Preliminary Technical Data EQUIVALENT CIRCUITS AVDD AD9271 AVDD VCM 15k LI-x, LG-x 06304-073 SDIO 350 Figure 5. Equivalent LNA Input Circuit Figure 8. Equivalent SDIO Input Circuit DRVDD AVDD V LO-x, LOSW-x 10 V DOUT+ V DOUT- V 06304-075 DRGND Figure 6. Equivalent LNA Output Circuit Figure 9. Equivalent Digital Output Circuit 10 CLK+ 10k 1.25V 10k 10 CLK- SCLK OR PDWN OR STBY 1k 30k 06304-007 06304-009 06304-008 30k Figure 7. Equivalent Clock Input Circuit Figure 10. Equivalent SCLK Input Circuit Rev. PrA | Page 15 of 58 06304-010 AD9271 AVDD Preliminary Technical Data RBIAS 100 AVDD VREF 06304-011 6k Figure 11. Equivalent RBIAS Circuit Figure 14. Equivalent VREF Circuit AVDD 70k CSB 1k 50 GAIN 06304-014 06304-012 Figure 12. Equivalent CSB Input Circuit Figure 15. Equivalent GAIN Input Circuit SENSE 1k CWDx+, CWDx- 10 Figure 13. Equivalent SENSE Circuit 06304-013 Figure 16. Equivalent CWD Output Circuit Rev. PrA | Page 16 of 58 06304-076 06304-074 Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS (fSAMPLE = 50 MSPS, AIN = 5 MHz, LPF = 1/3 x fSAMPLE, LNA gain = 6x) 2.00 AD9271 2000000 1800000 1.50 1600000 1.00 1400000 0.50 Absolute Error (dB) 85C 1200000 Number of Hits 1000000 0.00 25C -40C 800000 -0.50 600000 -1.00 400000 -1.50 200000 0 -2.00 0 0.1 0.2 0.3 0.4 0.5 Vgain (V) 0.6 0.7 0.8 0.9 1 -5 -4 -3 -2 -1 0 Codes 1 2 3 4 5 Figure 17. Absolute Gain Error vs. VGAIN at Three Temperatures Figure 20. Output-Referred Noise Histogram with Gain Pin at 0.0V, AD927150 1200000 1000000 800000 Number of Hits 600000 400000 200000 0 -5 -4 -3 -2 -1 0 Codes 1 2 3 4 5 Figure 18. Gain Error Histogram Figure 21. Output-Referred Noise Histogram with Gain Pin at 1.0V, AD927150 4.5 4 3.5 Input-referred Noise (nV/sqrt-Hz) 3 2.5 2 LNA Gain = 5x 1.5 LNA Gain = 6x LNA Gain = 8x 1 0.5 Figure 19. Gain Match Histogram for VGAIN = 0.2 V and 0.7 V 0 0 5 10 Frequency (MHz) 15 20 25 Figure 22. Short-Circuit, Input-Referred Noise vs. Frequency Rev. PrA | Page 17 of 58 AD9271 -99 0 Preliminary Technical Data -5 -100 LNA Gain = 5x -101 Output-referred Noise (dBFS/rt-Hz) LNA Gain = 6x LNA Gain = 8x -10 -3dB line -102 -15 Fundamental (dBFS) (1/3)*50MHz -103 -20 (1/3)*40MHz -104 -25 -105 (1/3)*25MHz -30 -106 -107 -35 -108 0 0.1 0.2 0.3 0.4 0.5 Vgain (V) 0.6 0.7 0.8 0.9 1 -40 0 2.5 5 7.5 10 12.5 Frequency (MHz) 15 17.5 20 22.5 25 Figure 23. Short-Circuit, Output-Referred Noise vs. VGAIN 66 Figure 26. Antialiasing Filter (AAF) Pass-Band Response 400 64 350 300 62 SNR (dBFS) SINAD (dB) SINAD (dBFS) 250 Group Delay (n s) SNR/SINAD 60 200 58 150 56 100 Vgain = 0.0 V Vgain = 0.5 V 54 50 Vgain = 1.0 V 52 0 0.1 0.2 0.3 0.4 0.5 Vgain (V) 0.6 0.7 0.8 0.9 1 0 0.1 1 Analog Input Frequency (MHz) 10 100 Figure 24. SNR/SINAD vs. Gain -50 1.7 Figure 27. Antialiasing Filter (AAF) Group Delay Response -55 1.65 -60 Input-referred noise (nV/rt-Hz) 1.6 -65 H2 (dBFS) Vgain=0.2V 1.55 Vgain=1V -70 1.5 -75 Vgain=0.5V 1.45 -80 -85 1.4 -40 -20 0 20 40 60 80 2 4 6 8 Fin (MHz) 10 12 14 16 Temperature (C) Figure 25. Short-Circuit, Input-Referred Noise vs. Temperature Figure 28. Second-Order Harmonic Distortion vs. Frequency Rev. PrA | Page 18 of 58 Preliminary Technical Data -50 AD9271 -40 -55 -50 -60 -60 Third Harmonic (dBFS) Vgain=0V -65 H3 (dBFS) Vgain=1V Vgain=0.5V -70 Vgain=0.5V Vgain=1V -70 -80 -90 -75 -100 -80 Vgain=0.2V -110 -85 2 4 6 8 Fin (MHz) -40 10 12 14 16 -35 -30 -25 -20 -15 -10 -5 0 ADC Output Level (dBFS) Figure 29. Third-Order Harmonic Distortion vs. Frequency -40 Figure 31. Third-Order Harmonic Distortion vs. ADC Output Level -50 -60 Second Harmonic (dBFS) -70 Vgain=0V Vgain=0.5V Vgain=1V -80 -90 -100 -110 -40 -35 -30 -25 -20 -15 -10 -5 0 ADC Output Level (dBFS) Figure 30. Second-Order Harmonic Distortion vs. ADC Output Level Rev. PrA | Page 19 of 58 AD9271 THEORY OF OPERATION ULTRASOUND The primary application for the AD9271 is medical ultrasound. Figure 32 shows a simplified block diagram of an ultrasound system. A critical function of an ultrasound system is the time gain control (TGC) compensation for physiological signal attenuation. Because the attenuation of ultrasound signals is exponential with respect to distance (time), a linear-in-dB VGA is the optimal solution. Key requirements in an ultrasound signal chain are very low noise, active input termination, fast overload recovery, low power, and differential drive to an ADC. Because ultrasound machines use beam-forming techniques requiring large binaryweighted numbers (for example, 32 to 512) of channels, the lowest power at the lowest possible noise is of key importance. Preliminary Technical Data Most modern machines use digital beam forming. In this technique, the signal is converted to digital format immediately following the TGC amplifier; beam forming is done digitally. The ADC resolution of 12 bits with up to 50 MSPS sampling satisfies the requirements of both general-purpose and highend systems. Power consumption and low cost are of primary importance in low-end and portable ultrasound machines, and the AD9271 is designed for these criteria. For additional information regarding ultrasound systems, refer to "How Ultrasound System Considerations Influence Front-End Component Choice," Analog Dialogue, Volume 36, Number 3, May-July 2002. TX HV AMPs TX BEAMFORMER BEAMFORMER CENTRAL CONTROL MULTICHANNEL TGC USES MANY VGAs AD9271 HV MUX/ DEMUX T/R SWITCHES LNA VGA AAF CW TRANSDUCER ARRAY 128, 256 ETC. ELEMENTS BIDIRECTIONAL CABLE TGC TIME GAIN COMPENSATION CW (ANALOG) BEAMFORMER SPECTRAL DOPPLER PROCESSING MODE IMAGE AND MOTION PROCESSING (B MODE) COLOR DOPPLER (PW) PROCESSING (F MODE) ADC Rx BEAMFORMER (B AND F MODES) Figure 32. Simplified Ultrasound System Block Diagram Rev. PrA | Page 20 of 58 06304-077 AUDIO OUTPUT DISPLAY Preliminary Technical Data RFB1 CFB RFB2 CS CSH RS CLG LG-X LO-X AD9271 gm TO SWITCH ARRAY CDW+ CDW- LOSW-X LI-X LNA ATTENUATOR -30dB TO 0dB +24dB AAF 12-BIT PIPELINE ADC SERIAL LVDS DOUT + X DOUT - X GAIN INTERPOLATOR SERIAL PORT INTERFACE AD9271 SCLK GAIN+ GAIN- SDIO CSB Figure 33. Simplified Block Diagram of Single Channel CHANNEL OVERVIEW Each channel contains both a TGC and CW Doppler signal path. Common to both signal paths, the LNA provides useradjustable input impedance termination. The CW Doppler path includes a transconductance amplifier and crosspoint switch. The TGC path includes a differential X-AMP(R) VGA, an antialiasing filter, and an ADC. Figure 33 shows a simplified block diagram with external components. The signal path is fully differential throughout to maximize signal swing and reduce even-order distortion; however, the LNA is designed to be driven from a single-ended signal source. The LNA supports differential output voltages as high as 2 V p-p with positive and negative excursions of 0.5 V from a common-mode voltage of 0.9 V. The LNA differential gain sets the maximum input signal before saturation. One of three gains is set through the SPI. The corresponding input full-scale for the gain settings of 5, 6, or 8 is 400 mV p-p, 333 mV p-p, and 250 mV p-p, respectively. Overload protection ensures quick recovery time from large input voltages. Because the inputs are capacitively coupled to a bias voltage near midsupply, very large inputs can be handled without interacting with the ESD protection. Low value feedback resistors and the current-driving capability of the output stage allow the LNA to achieve a low input-referred noise voltage of 1.2 nV/Hz. This is achieved with a current consumption of only 16 mA per channel (30 mW). On-chip resistor matching results in precise single-ended gains critical for accurate impedance control. The use of a fully differential topology and negative feedback minimizes distortion. Low HD2 is particularly important in second harmonic ultrasound imaging applications. Differential signaling enables smaller swings at each output, further reducing third-order distortion. Low Noise Amplifier (LNA) Good noise performance relies on a proprietary ultralow noise LNA at the beginning of the signal chain, which minimizes the noise contribution in the following VGA. Active impedance control optimizes noise performance for applications that benefit from input impedance matching. A simplified schematic of the LNA is shown in Figure 34. LI-x is capacitively coupled to the source. An on-chip bias generator establishes dc input bias voltages of around 1.4 V and centers the output common-mode levels at 0.9 V (VDD/2). A capacitor, CLG, of the same value as the input coupling capacitor, CS, is connected from the LG-x pin to ground. CFB RFB1 RFB2 LOSW LO-X CS RS LI-X CSH LG-X CLG 06304-101 Active Impedance Matching The LNA consists of a single-ended voltage gain amplifier with differential outputs and the negative output externally available. For example, with a fixed gain of 6 (15.6 dB), an active input termination is synthesized by connecting a feedback resistor between the negative output pin, LO-x, and the positive input pin, LI-x. This technique is well known and results in the input resistance shown in Equation 2, where A/2 is the single-ended gain or the gain from the LI-x inputs to the LO-x outputs. R IN = R FB (1 + A 2) 06304-071 (2) Figure 34. Simplified LNA Schematic Rev. PrA | Page 21 of 58 AD9271 Because the amplifier has a gain of 6x from its input to its differential output, it is important to note that the gain A/2 is the gain from Pin LI-x to Pin LO-x, and is 6 dB less than the gain of the amplifier, or 9.6 dB (3x). The input resistance is reduced by an internal bias resistor of 15 k in parallel with the source resistance connected to Pin LI-x, with Pin LG-x ac grounded. Equation 3 can be used to calculate the needed RFB for a desired RIN, even for higher values of RIN. RIN = RFB || 15 k (1+ 3) Preliminary Technical Data CFB is needed in series with RFB because the dc levels at Pin LO-x and Pin LI-x are unequal. Table 7. Active Termination External Component Values LNA Gain 5x 6x 8x 5x 6x 8x 5x 6x 8x RIN () 50 50 50 100 100 100 200 200 200 RFB () 175 200 250 350 400 500 700 800 1000 Minimum CSH (pF) 90 70 50 30 20 10 na na na BW (MHz) 49 59 73 49 59 73 49 49 49 (3) For example, to set RIN to 200 , the value of RFB is 845 . If the simplified equation, Equation 2, is used to calculate RIN, the resulting value is 190 , resulting in a less than 0.1 dB gain error. Factors such as a dynamic source resistance might influence the absolute gain accuracy more significantly. At higher frequencies, the input capacitance of the LNA needs to be considered. The user must determine the level of matching accuracy and adjust RFB accordingly. The bandwidth (BW) of the LNA is about 70 MHz. Ultimately the BW of the LNA limits the accuracy of the synthesized RIN. For RIN = RS up to about 200 , the best match is between 100 kHz and 10 MHz, where the lower frequency limit is determined by the size of the ac-coupling capacitors, and the upper limit, by the LNA BW. Furthermore, the input capacitance and RS limit the BW at higher frequencies. 1k RIN = 500, RFB = 2.5k RSH = LNA Noise The short-circuit noise voltage (input-referred noise) is an important limit on system performance. The short-circuit noise voltage for the LNA is 1.2 nV/Hz or 1.4 nV/Hz (at maximum gain), including the VGA noise. These measurements, which are taken without a feedback resistor, provide the basis for calculating the input noise and noise figure performance of the configurations shown in Figure 43. Figure 43 and Figure 44 are simulations of noise figure vs. RS results using these configurations and an input-referred noise voltage for the VGA of 4 nV/Hz. Unterminated (RFB = ) operation exhibits the lowest equivalent input noise and noise figure. Figure 44 shows the noise figure vs. source resistance rising at low RS--where the LNA voltage noise is large compared with the source noise-- and at high RS due to current noise. UNTERMINATED RIN , CSH = 0 pF INPUT IMPEDANCE () RIN = 200, RFB = 1k RS RSH = 50, CSH = 22 pF 100 RIN = 100, RFB = 499 VIN + - RESISTIVE TERMINATION RS RIN RS VOUT RIN = 50, RFB = 249 RSH = , CSH = 0 pF RSH = 50, CSH = 22 pF VIN + - VOUT 10 100k 1M FREQUENCY (Hz) 10M 50M ACTIVE IMPEDANCE MATCH RFB R RS VIN + - RFB 1 + A/2 03199-079 Figure 35. RIN vs. Frequency for Various Values of RFB (Effects of RSH and CSH are Also Shown IN Figure 35 shows RIN vs. frequency for various values of RFB. Note that at the lowest value, 50 , RIN peaks at frequencies greater than 10 MHz. This is due to the BW roll-off of the LNA as mentioned earlier. However, as can be seen for larger RIN values, parasitic capacitance starts rolling off the signal BW before the LNA can produce peaking. CSH further degrades the match; therefore, CSH should not be used for values of RIN that are greater than 100 . Table 7 lists the recommended values for RFB and CSH in terms of RIN. Rev. PrA | Page 22 of 58 VOUT RIN = Figure 36. Input Configurations Preliminary Technical Data 7 INCLUDES NOISE OF VGA 6 5 4 3 ACTIVE IMPEDANCE MATCH 2 1 SIMULATION 0 50 100 UNTERMINATED 1k RS () RESISTIVE TERMINATION (RS = RIN) AD9271 INPUT OVERDRIVE Excellent overload behavior is of primary importance in ultrasound. Both the LNA and VGA have built-in overdrive protection and quickly recover after an overload event. NOISE FIGURE (dB) Input Overload Protection As with any amplifier, voltage clamping prior to the inputs is highly recommended if the application is subject to high transient voltages. A block diagram of a simplified ultrasound transducer interface is shown in Figure 39. A common transducer element serves the dual functions of transmitting and receiving ultrasound energy. During the transmitting phase, high voltage pulses are applied to the ceramic elements. A typical transmit/receive (T/R) switch may consist of four high voltage diodes in a bridge configuration. Although the diodes ideally block transmit pulses from the sensitive receiver input, diode characteristics are not ideal, and resulting leakage transients imposed on the LI-x inputs can be problematic. Because ultrasound is a pulse system and time-of-flight is used to determine depth, quick recovery from input overloads is essential. Overload can occur in the preamp and the VGA. Immediately following a transmit pulse, the typical VGA gains are low, and the LNA is subject to overload from T/R switch leakage. With increasing gain, the VGA can become overloaded due to strong echoes that occur near field echoes and acoustically dense materials, such as bone. Figure 39 illustrates an external overload protection scheme. A pair of back-to-back Schottky diodes is installed prior to installing the ac-coupling capacitors. Although the BAS40 diodes are shown, any diode is prone to exhibiting some amount of shot noise. Many types of diodes are available for achieving the desired noise performance. The configuration shown in Figure 39 tends to add 2 nVHz of input-referred noise. Decreasing the 5 k resistor and increasing the 2 k resistor may improve noise contribution, depending on the application. With the diodes shown in Figure 39, clamping levels of 0.5 V or less significantly enhances the system overload performance. +5V Tx DRIVER 5k Figure 37. Noise Figure vs. RS for Resistive, Active Matched and Unterminated Inputs, Gain = 1 V 7 INCLUDES NOISE OF VGA 6 5 4 3 2 1 SIMULATION 0 50 100 RS () NOISE FIGURE (dB) RIN = 50 RIN = 75 RIN = 100 RIN = 200 RFB = 03199-077 1k Figure 38. Noise Figure vs. RS for Various Fixed Values of RIN, Actively Matched, Gain = 1 V. The primary purpose of input impedance matching is to improve the system transient response. With resistive termination, the input noise increases due to the thermal noise of the matching resistor and the increased contribution of the LNA's input voltage noise generator. With active impedance matching, however, the contributions of both are smaller than they would be for resistive termination by a factor of 1/(1 + LNA Gain). Figure 37 shows the relative noise figure (NF) performance. In this graph, the input impedance was swept with RS to preserve the match at each point. The noise figures for a source impedance of 50 are 7.1 dB, 4.1 dB, and 2.5 dB for the resistive, active, and unterminated configurations, respectively. The noise figures for 200 are 4.6 dB, 2.0 dB, and 1.0 dB, respectively. Figure 38 shows the NF vs. RS for various values of RIN, which is helpful for design purposes. The plateau in the NF for actively matched inputs mitigates source impedance variations. For comparison purposes, a preamp with a gain of 15.6 dB and noise spectral density of 1.2 nV/Hz, combined with a VGA with 4 nV/Hz, yields a noise figure degradation of approximately 1.5 dB (for most input impedances), which is significantly worse than the AD9271 performance. 03199-076 HV BAS40-04 10nF AD9271 LNA 5k TRANSDUCER -5V 2k 10nF 06304-100 Figure 39. Input Overload Protection CW DOPPLER OPERATION Modern ultrasound machines used for medical applications employ a 2n binary array of receivers for beam forming, with Rev. PrA | Page 23 of 58 AD9271 typical array sizes of 16 or 32 receiver channels phase-shifted and summed together to extract coherent information. When used in multiples, the desired signals from each of the channels can be summed to yield a larger signal (increased by a factor N, where N is the number of channels), and the noise is increased by the square root of the number of channels. This technique enhances the signal-to-noise performance of the machine. The critical elements in a beam-former design are the means to align the incoming signals in the time domain and the means to sum the individual signals into a composite whole. Beam forming, as applied to medical ultrasound, is defined as the phase alignment and summation of signals that are generated from a common source but received at different times by a multielement ultrasound transducer. Beam forming has two functions: It imparts directivity to the transducer, enhancing its gain, and it defines a focal point within the body from which the location of the returning echo is derived. AD9271 LNA Preliminary Technical Data The AD9271 includes the front-end components needed to implement analog beam forming for CW Doppler operation. These components allow CW channels with similar phases to be coherently combined before phase alignment and down mixing, thus reducing the number of delay lines or adjustable phase shifters/down mixers (AD8333 or AD8339) required. Next, if delay lines are used, the phase alignment is performed and then the channels are coherently summed and down converted by a dynamic range I/Q demodulator. Alternatively, if phase shifters/ down mixers, such as the AD8333 and AD8339, are used, phase alignment and down conversion are done before coherently summing all channels into I/Q signals. In either case, the resultant I and Q signals are filtered and sampled by two high resolution ADCs, and the sampled signals are processed to extract the relevant Doppler information. gm gm SWITCH ARRAY LNA 8 x CHANNEL LNA AD8333 2.5V 600nH 600nH 700 gm gm LNA 2.5V 600nH 600nH 700 8 x AD9271 3 x AD8333 AD9271 LNA AD8333 2.5V 600nH 600nH 600nH 2.5V SWITCH ARRAY 600nH 700 I OPA 700 gm gm LNA 8 x CHANNEL LNA gm Q 16-BIT ADC 06304-096 LNA gm OPA 16-BIT ADC Figure 40. Typical CW Doppler System Using the AD9271 and AD8339 Rev. PrA | Page 24 of 58 Preliminary Technical Data Crosspoint Switch Each LNA is followed by a transconductance amp for V/I conversion. Currents can be routed to one of six pairs of differential outputs or to 12 single-ended outputs for summing. Each CWD output pin sinks 2.4 mA dc current, and the signal has a full-scale of 2 mA for each channel selected by the cross-point switch. For example, if four channels were to be summed on one CWD output, the output would sink 9.6 mA dc and have a full-scale current output of 8 mA. The maximum number of channels combined must be considered in setting the load impedance for I/V conversion to ensure that the full-scale swing and commonmode voltage are within the operating limits of the AD9271. When interfacing to the AD8339, a common-mode voltage of 2.5 V and a full-scale swing of 2.8 V p-p are desired This can be accomplished by connecting an inductor between each CWD output and a 2.5 V supply, and then connecting either a singleended or differential load resistance to the CWD outputs. The value of resistance should be calculated based on the maximum number of channels that can be combined. CWD outputs are required under full-scale swing to be within 1.5 V and CWVDD (3.3 V supply). Table 9. ADC Specifications ADC Parameters FS/FSrms (Vpp/mV) SNR (dB) ENOB (Bits) SFDR (dB) Noise (rms uV/nV/rt(Hz)) Specifications 2/707 70 11.3 -82 194/50 AD9271 In summary, the maximum gain required is determined by (ADC Noise Floor/VGA Input Noise Floor) + Margin = 20 log(194/4.7) + 10 dB = 42.3 dB The minimum gain required is determined by (ADC Input FS/VGA Input FS) + Margin = 20 log(2/0.333) - 6 dB = 9.6 dB Therefore, a 12-bit, 40 MSPS ADC with 15 MHz of bandwidth should suffice in achieving the dynamic range required for most ultrasound systems today. The system gain is distributed as listed in Table 7. Table 10. Channel Gain Distribution Section LNA Attenuator VGA Amp Filter ADC Total Nominal Gain (dB) 14/15.6/18 0 to -30 25 0 0 9 to 39/10.6 to 40.6/13 to 43 TGC OPERATION The signal path is fully differential throughout to maximize signal swing and reduce even-order distortion; however, the LNAs are designed to be driven from a single-ended signal source. Gain values are referenced from the single-ended LNA input to the differential output of the LNA. A simple exercise in understanding the maximum and minimum gain requirements is shown in Figure 41. Table 8. LNA Specifications LNA Parameters BW (MHz) FS/FSrms (mVpp/mV) SNR (dB) ENOB (Bits) Noise (rms uV/nV/rt(Hz)) MINIMUM GAIN Specifications 15 333/118 88.1 14.3 4.65/1.2 The linear-in-dB gain range of the TGC path is 30 dB, extending from 9.6 dB to 39.6 dB. The slope of the gain control interface is 30 dB/V, and the gain control range is 0 V to 1 V. Equation 1 is the expression for gain. Gain (dB ) = 30 dB VGAIN + ICPT V (1) where ICPT is the intercept point of the LNA gain. ADC FS (2V p-p) LNA FS (0.333V p-p SE) 70dB ADC EQUIVALENT DYNAMIC RANGE 88dB ADC NOISE FLOOR (194V rms) MAXIMUM GAIN VGA NOISE FLOOR (4.7V rms) In its default condition, the LNA has a gain of 15.6 dB (6x) and the VGA gain is -6 dB if the voltage on the VGAIN pin is 0 V. This gives rise to a total gain (or ICPT) of 9.6 dB through the TGC path if the LNA input is unmatched, or of 3.6 dB if the LNA is matched to 50 (RFB = 200 ). If the voltage on the VGAIN pin is 1 V, however, the VGA gain is 24 dB. This gives rise to a total gain of 39.6 dB through the TGC path if the LNA input is unmatched, or of 33.5 dB if the LNA input is matched. Each of the LNA outputs is dc-coupled to a VGA input. The VGA consists of an attenuator with a range of 30 dB followed by an amplifier with 24 dB of gain for a net gain range of -5 dB to +25 dB. The X-AMP gain-interpolation technique results in low Figure 41. Gain Requirements of TGC for a 12-Bit, 40 MSPS ADC Rev. PrA | Page 25 of 58 06304-097 AD9271 gain error and uniform bandwidth, and differential signal paths minimize distortion. At low gain the VGA should limit the system noise performance (SNR), whereas at high gains the noise is defined by the source and LNA. The maximum voltage swing is bounded by the fullscale peak-to-peak ADC input voltage (2 V p-p). Preliminary Technical Data Gain Control The gain control interface, GAIN+, is a differential input. VGAIN varies the gain of all VGAs through the interpolator by selecting the appropriate input stages connected to the input attenuator. The nominal VGAIN range for 30 dB/V is 0 V to 1 V, with the best gain-linearity from about 0.1 V to 0.9 V, where the error is typically less than 0.2 dB. For VGAIN voltages greater than 0.9 V and less than 0.1 V, the error increases. The value of the VGAIN voltage can be increased to that of the supply voltage without gain foldover. Gain control response time is less than 750 ns to settle within 10% of the final value for a change from minimum to maximum gain. There are two ways in which the GAIN pins can be interfaced. Using a single-ended method, a Kelvin type of connection to ground should be used as shown in Figure 43. For driving multiple devices, it is preferred to use a differential method as shown in Figure 44. In either method, the GAIN pins should be dc-coupled and driven to accommodate a 1 V full-scale input. Variable Gain Amplifier The differential X-AMP VGA provides precise input attenuation and interpolation. It has a low input-referred noise of 4 nV/Hz and excellent gain linearity. A simplified block diagram is shown in Figure 42. GAIN GAIN INTERPOLATOR + gm VIP 3dB POSTAMP VIN - POSTAMP Figure 42. Simplified VGA Schematic Figure 43. Single-Ended Gain Pin Configuration The input of the VGA is a 12-stage differential resistor ladder with 3.01 dB per tap. The resulting total gain range is 30 dB, which allows for range loss at the endpoints. The effective input resistance per side is 180 nominally for a total differential resistance of 360 . The ladder is driven by a fully differential input signal from the LNA. LNA outputs are dc-coupled to avoid external decoupling capacitors. The common-mode voltage of the attenuator and the VGA is controlled by an amplifier that uses the same midsupply voltage derived in the LNA, permitting dc coupling of the LNA to the VGA without introducing large offsets due to commonmode differences. However, any offset from the LNA will be amplified as the gain is increased, producing an exponentially increasing VGA output offset. The input stages of the X-AMP are distributed along the ladder, and a biasing interpolator, controlled by the gain interface, determines the input tap point. With overlapping bias currents, signals from successive taps merge to provide a smooth attenuation range from 0 dB to -30 dB. This circuit technique results in linear-in-dB gain law conformance and low distortion levels--only deviating 0.2 dB or less from the ideal. The gain slope is monotonic with respect to the control voltage and is stable with variations in process, temperature, and supply. The X-AMP inputs are part of a 25 dB gain feedback amplifier that completes the VGA. Its bandwidth is about 80 MHz. The input stage is designed to reduce feedthrough to the output and to ensure excellent frequency response uniformity across the gain setting. 06304-078 499 AVDD 499 0.5V CM 523 10k 06304-098 AD9271 GAIN+ 100 0.01F 0.25DC AT 0.5V CM 26k 0.5V DC 50 AD8318 0.25DC AT 0.5V CM 499 GAIN- 100 0.01F Figure 44. Differential Gain Pin Configuration VGA Noise In a typical application, a VGA compresses a wide dynamic range input signal to within the input span of an ADC. The input-referred noise of the LNA limits the minimum resolvable input signal, whereas the output-referred noise, which depends primarily on the VGA, limits the maximum instantaneous dynamic range that can be processed at any one particular gain control voltage. This limit is set in accordance with the quantization noise floor of the ADC. Output- and input-referred noise as a function of VGAIN are shown in Figure TBD and Figure TBD for the short-circuited input conditions. The input noise voltage is simply equal to the output noise divided by the measured gain at each point in the control range. The output-referred noise is a flat 65 nV/Hz over most of the gain range, because it is dominated by the fixed output-referred noise of the VGA. At the high end of the gain control range, the Rev. PrA | Page 26 of 58 Preliminary Technical Data noise of the LNA and source prevail. The input-referred noise reaches its minimum value near the maximum gain control voltage, where the input-referred contribution of the VGA is miniscule. At lower gains, the input-referred noise, and therefore the noise figure, increases as the gain decreases. The instantaneous dynamic range of the system is not lost, however, because the input capacity increases as the input-referred noise increases. The contribution of the ADC noise floor has the same dependence. The important relationship is the magnitude of the VGA output noise floor relative to that of the ADC. Gain control noise is a concern in very low noise applications. Thermal noise in the gain control interface can modulate the channel gain. The resultant noise is proportional to the output signal level and usually only evident when a large signal is present. The gain interface includes an on-chip noise filter, which reduces this effect significantly at frequencies above 5 MHz. Care should be taken to minimize noise impinging at the GAIN input. An external RC filter can be used to remove VGAIN source noise. The filter bandwidth should be sufficient to accommodate the desired control bandwidth. AD9271 Tuning is normally off to avoid changing the capacitor settings during critical times. The tuning circuit is enabled and disabled through the SPI. Tuning should be done after initial power-up and after reprogramming the filter cutoff scaling or ADC sample rate. Occasional retuning during an idle time is recommended. Antialiasing Filter The filter that the signal reaches prior to the ADC is used to reject dc signals and to bandlimit the signal for antialiasing. Figure 45 shows the architecture of the filter. 4k 1C* 56/112pF 2k 2k 2k 7.5C* 2k 56/112pF 2k 6.5C* 2k 4k *C = 0.5 TO 3.1pF Figure 45. Simplified Filter Schematic The filter can be configured for dc coupling or to have a single pole for high-pass filtering at either 700 kHz or 350 kHz (programmed through the SPI). The high-pass pole, however, is not tuned and can vary by 30%. A third-order Butterworth low-pass filter is used to reduce noise bandwidth and provide antialiasing for the ADC. The filter uses on-chip tuning to trim the capacitors to set the desired cutoff and reduce variation. The default -3dB cutoff is 1/3 the ADC sample clock rate. The cutoff can be scaled to 0.7, 0.8, 0.9, 1, 1.1, 1.2, or 1.3 times this frequency through the SPI. The cutoff can be set from 8 MHz to 18 MHz. Rev. PrA | Page 27 of 58 06304-099 1C* AD9271 A/D CONVERTER The AD9271 architecture consists of a pipelined ADC that is divided into three sections: a 4-bit first stage followed by eight 1.5-bit stages and a 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stages. The quantized outputs from each stage are combined into a 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on preceding samples. Sampling occurs on the rising edge of the clock. Each stage except for the last of the pipeline consists of a low resolution flash ADC connected to a switched-capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage consists of a flash ADC. The output staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The data is then serialized and aligned to the frame and output clock. 3.3V VFAC3 OUT EN 0.1F Preliminary Technical Data AD951x FAMILY 0.1F CLK PECL DRIVER CLK 50* *50 CLK+ 100 0.1F 240 06304-051 0.1F ADC AD9271 CLK- 240 RESISTOR IS OPTIONAL. Figure 47. Differential PECL Sample Clock 3.3V VFAC3 OUT EN 0.1F AD951x FAMILY CLK LVDS DRIVER CLK 0.1F CLK+ 100 0.1F 0.1F 50 * *50 ADC AD9271 CLK- 06304-052 RESISTOR IS OPTIONAL. Figure 48. Differential LVDS Sample Clock CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9271 sample clock inputs (CLK+ and CLK-) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ and CLK- pins via a transformer or capacitors. These pins are biased internally and require no additional bias. Figure 46 shows the preferred method for clocking the AD9271. The low jitter clock source, such as the Valpey Fisher oscillator VFAC3-BHL-50MHz, is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the secondary transformer limit clock excursions into the AD9271 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9271 and preserves the fast rise and fall times of the signal, which are critical to low jitter performance. 3.3V MINI-CIRCUITS ADT1-1WT, 1:1Z 0.1F XFMR 0.1F 0.1F SCHOTTKY DIODES: HSM2812 In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be driven directly from a CMOS gate, and the CLK- pin should be bypassed to ground with a 0.1 F capacitor in parallel with a 39 k resistor (see Figure 48). Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages up to 3.3 V, making the selection of the drive logic voltage very flexible. 3.3V VFAC3 OUT EN 0.1F CLK AD951x FAMILY OPTIONAL 0.1F 100 50* CMOS DRIVER CLK CLK+ 0.1F ADC AD9271 CLK- 06304-053 0.1F *50 RESISTOR IS OPTIONAL. 39k Figure 49. Single-Ended 1.8 V CMOS Sample Clock 3.3V 0.1F OUT EN VFAC3 CLK AD951x FAMILY OPTIONAL 0.1F 100 50 * CMOS DRIVER CLK CLK+ 0.1F EN OUT VFAC3 CLK+ 50 100 CLK- 06304-050 *50 RESISTOR IS OPTIONAL. Figure 50. Single-Ended 3.3 V CMOS Sample Clock Figure 46. Transformer-Coupled Differential Clock Clock Duty Cycle Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to the clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9271 contains a duty cycle If a low jitter clock is available, another option is to ac-couple a differential PECL signal to the sample clock input pins as shown in Figure 47. The AD951x family of clock drivers offers excellent jitter performance. Rev. PrA | Page 28 of 58 06304-054 ADC AD9271 0.1F 0.1F ADC AD9271 CLK- Preliminary Technical Data stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9271. When the DCS is on, noise and distortion performance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See the Memory Map section for more details on using this feature. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new rate. AD9271 Clock Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by SNR Degradation = 20 x log 10[1/2 x x fA x tJ] In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter. IF undersampling applications are particularly sensitive to jitter (see Figure 51). The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9271. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources, such as the Valpey Fisher VFAC3 series. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about jitter performance as it relates to ADCs (visit www.analog.com). 130 120 110 100 16 BITS 14 BITS 12 BITS 10 BITS 8 BITS 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps 10 100 ANALOG INPUT FREQUENCY (MHz) 1000 06304-038 RMS CLOCK JITTER REQUIREMENT SNR (dB) 90 80 70 60 50 40 30 1 Figure 51. Ideal SNR vs. Input Frequency and Jitter Rev. PrA | Page 29 of 58 AD9271 Power Dissipation and Power-Down Mode As shown in Figure 52, the power dissipated by the AD9271 is proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. 800 Preliminary Technical Data In power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, PLL, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering power-down mode and must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in the power-down mode; shorter cycles result in proportionally shorter wake-up times. With the recommended 0.1 F and 4.7 F decoupling capacitors on REFT and REFB, it takes approximately 1 sec to fully discharge the reference buffer decoupling capacitors and xx s to restore full operation. There are a number of other power-down options available when using the SPI port interface. The user can individually power down each channel or put the entire device into standby mode. This allows the user to keep the internal PLL powered up when fast wake-up times (~xxx ns) are required. See the Memory Map section for more details on using these features. 20 30 Sampling Frequency (MSPS) 700 600 500 Currents (mA) 400 300 25MSPS Speed Grade 40MSPS Speed Grade 50MSPS Speed Grade IDRVDD 200 100 0 0 10 40 50 60 Digital Outputs and Timing The AD9271 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option similar to the IEEE 1596.3 standard using the SDIO/ODM pin or via the SPI. This LVDS standard can further reduce the overall power dissipation of the device by approximately xx mW. See the SDIO Pin section or Table 16 in the Memory Map section for more information. The LVDS driver current is derived on-chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. The AD9271 LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 termination resistor placed as close to the receiver as possible. No far-end receiver termination and poor differential trace routing may result in timing errors. It is recommended that the trace length is no longer than 24 inches and that the differential output traces are kept close together and at equal lengths. An example of the FCO and data stream with proper trace length and position can be found in Figure 54. Figure 52. Supply Current vs. fSAMPLE for fIN = 7.5 MHz 190 180 170 160 Power/channel (mW) 150 140 130 120 25MSPS Speed Grade 40MSPS Speed Grade 50MSPS Speed Grade 110 100 0 10 20 30 40 50 60 Sampling Frequency (MSPS) Figure 53. Power per Channel vs. fSAMPLE for fIN = 7.5 MHz By asserting the PDWN pin high, the AD9271 is placed in power-down mode. In this state, the ADC typically dissipates xx mW. During power-down, the LVDS output drivers are placed in a high impedance state. The AD9271 returns to normal operating mode when the PDWN pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant. By asserting the STBY pin high, the AD9271 is placed in a standby mode. In this state, the ADC typically dissipates xx mW. During standby, the entire part is powered down except the internal references. The LVDS output drivers are placed in a high impedance state. This mode is well suited for applications that require power savings because it allows the device to be powered down when not in use and then quickly powered up. The time to power this device back up is also greatly reduced. The AD9271 returns to normal operating mode when the STBY pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant. Rev. PrA | Page 30 of 58 Preliminary Technical Data AD9271 Figure 54. LVDS Output Timing Example in ANSI Mode (Default) An example of the LVDS output using the ANSI standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths of less than 24 inches on regular FR-4 material is shown in Figure 55. Figure 56 shows an example of when the trace lengths exceed 24 inches on regular FR-4 material. Notice that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position; therefore, the user must determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. Additional SPI options allow the user to further increase the internal termination (and therefore increase the current) of all eight outputs in order to drive longer trace lengths (see Figure 57). Even though this produces sharper rise and fall times on the data edges, is less prone to bit errors, and improves frequency distribution (see Figure 57), the power dissipation of the DRVDD supply increases when this option is used. In cases that require increased driver strength to the DCO and FCO outputs because of load mismatch Register 15 allows the user to double the drive strength. To do this, set the appropriate bit in Register 5. Note that this feature cannot be used with Bit 4 and Bit 5 in Register 15 because these bits take precedence over this feature. See the Memory Map section for more details. Figure 56. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths of Greater than 24 Inches on Standard FR-4 Figure 57. Data Eye for LVDS Outputs in ANSI Mode with 100 Termination on and Trace Lengths of Greater than 24 Inches on Standard FR-4 The format of the output data is offset binary by default. An example of the output coding format can be found in Table 11. If it is desired to change the output data format to twos complement, see the Memory Map section. Table 11. Digital Output Coding Code 4095 2048 2047 0 (VIN+) - (VIN-), Input Span = 2 V p-p (V) +1.00 0.00 -0.000488 -1.00 Digital Output Offset Binary (D11 ... D0) 1111 1111 1111 1000 0000 0000 0111 1111 1111 0000 0000 0000 Data from each ADC is serialized and provided on a separate channel. The data rate for each serial stream is equal to 12 bits times the sample clock rate, with a maximum of 600 Mbps (12 bits x 50 MSPS = 600 Mbps). The lowest typical conversion rate is 10 MSPS. However, if lower sample rates are required for a specific application, the PLL can be set up for encode rates lower than 10 MSPS via the SPI. This allows encode rates as low as 5 MSPS. See the Memory Map section for details on enabling this feature. Figure 55. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths of Less than 24 Inches on Standard FR-4 Rev. PrA | Page 31 of 58 AD9271 Two output clocks are provided to assist in capturing data from the AD9271. The DCO is used to clock the output data and is equal to six times the sampling clock (CLK) rate. Data is clocked out of the AD9271 and must be captured on the rising and falling edges of the DCO that supports double data rate Preliminary Technical Data (DDR) capturing. The frame clock out (FCO) is used to signal the start of a new output byte and is equal to the sampling clock rate. See the timing diagram shown in Figure 2 for more information. Table 12. Flex Output Test Modes Output Test Mode Bit Sequence 0000 0001 Subject to Data Format Select N/A Yes Pattern Name Off (default) Midscale short 0010 +Full-scale short 0011 -Full-scale short 0100 Checkerboard 0101 0110 0111 PN sequence long1 PN sequence short1 One/zero word toggle 1000 1001 User input One/zero bit toggle 1010 1x sync 1011 One bit high 1100 Mixed frequency Digital Output Word 1 N/A 1000 0000 (8 bits) 10 0000 0000 (10 bits) 1000 0000 0000 (12 bits) 10 0000 0000 0000 (14 bits) 1111 1111 (8 bits) 11 1111 1111 (10 bits) 1111 1111 1111 (12 bits) 11 1111 1111 1111 (14 bits) 0000 0000 (8 bits) 00 0000 0000 (10 bits) 0000 0000 0000 (12 bits) 00 0000 0000 0000 (14 bits) 1010 1010 (8 bits) 10 1010 1010 (10 bits) 1010 1010 1010 (12 bits) 10 1010 1010 1010 (14 bits) N/A N/A 1111 1111 (8 bits) 11 1111 1111 (10 bits) 1111 1111 1111 (12 bits) 11 1111 1111 1111 (14 bits) Register 0x19 to Register 0x1A 1010 1010 (8 bits) 10 1010 1010 (10 bits) 1010 1010 1010 (12 bits) 10 1010 1010 1010 (14 bits) 0000 1111 (8 bits) 00 0001 1111 (10 bits) 0000 0011 1111 (12 bits) 00 0000 0111 1111 (14 bits) 1000 0000 (8 bits) 10 0000 0000 (10 bits) 1000 0000 0000 (12 bits) 10 0000 0000 0000 (14 bits) 1010 0011 (8 bits) 10 0110 0011 (10 bits) 1010 0011 0011 (12 bits) 10 1000 0110 0111 (14 bits) Digital Output Word 2 N/A Same Same Yes Same Yes 0101 0101 (8 bits) 01 0101 0101 (10 bits) 0101 0101 0101 (12 bits) 01 0101 0101 0101 (14 bits) N/A N/A 0000 0000 (8 bits) 00 0000 0000 (10 bits) 0000 0000 0000 (12 bits) 00 0000 0000 0000 (14 bits) Register 0x1B to Register 0x1C N/A No Yes Yes No No No N/A No N/A No N/A No 1 All test mode options, except PN Sequence Short and PN Sequence Long, can support 8- to 14-bit word lengths in order to verify data capture to the receiver. Rev. PrA | Page 32 of 58 Preliminary Technical Data When using the serial port interface (SPI), the DCO phase can be adjusted in 60 increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO timing, as shown in Figure 2, is 90 relative to the output data edge. An 8-, 10-, and 14-bit serial stream can also be initiated from the SPI. This allows the user to implement different serial streams and test the device's compatibility with lower and higher resolution systems. When changing the resolution to an 8- or 10-bit serial stream, the data stream is shortened. When using the 14-bit option, the data stream stuffs two 0s at the end of the normal 14-bit serial data. When using the SPI, all of the data outputs can also be inverted from their nominal state. This is not to be confused with inverting the serial stream to an LSB-first mode. In default mode, as shown in Figure 2, the MSB is represented first in the data output serial stream. However, this can be inverted so that the LSB is represented first in the data output serial stream (see Figure 3). There are 12 digital output test pattern options available that can be initiated through the SPI. This is a useful feature when validating receiver capture and timing. Refer to Table 12 for the output bit sequencing options available. Some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. It should be noted that some patterns may not adhere to the data format select option. In addition, customer user patterns can be assigned in the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode options, except PN Sequence Short and PN Sequence Long can support 8- to 14-bit word lengths in order to verify data capture to the receiver. The PN Sequence Short pattern produces a pseudorandom bit sequence that repeats itself every 29 - 1 or 511 bits. A description of the PN sequence and how it is generated can be found in section 5.1 of the ITU-T 0.150 (05/96) standard. For the AD9271, the only discrepancy from the ITU standard is that the starting value is a specific value instead of all ones. See Table 10 for initial values. The PN Sequence Long pattern produces a pseudorandom bit sequence that repeats itself every 223 - 1 or 8,388,607 bits. A description of the PN sequence and how it is generated can be found in section 5.6 of the ITU-T 0.150 (05/96) standard. The only two discrepancies between the ITU standard and the AD9271 PN Sequence Long implementation are as follows. First, the starting value is a specific value instead of all ones. Second, the AD9271 inverts the bit stream with relation to the ITU standard. See Table 10 for initial values. Table 10. PN Sequence Initial Value AD9271 First 3 output samples (MSB 1st) 0xdf9, 0x353, 0x301 PN Sequence Short 0x0df PN Sequence Long 0x29b80a 0x591, 0xfd7, 0a3 Consult the Memory Map section for information on how to change these additional digital output timing features through the serial port interface or SPI. SDIO Pin This pin is required to operate the SPI port interface. It has an internal 30 k pull-down resistor that pulls this pin low and is only 1.8 V tolerant. If applications require that this pin be driven from a 3.3 V logic level, insert a 1 k resistor in series with this pin to limit the current. SCLK Pin This pin is required to operate the SPI port interface. It has an internal 30 k pull-down resistor that pulls this pin low and is both 1.8 V and 3.3 V tolerant. CSB Pin This pin is required to operate the SPI port interface. It has an internal 70 k pull-down resistor that pulls this pin low and is both 1.8 V and 3.3 V tolerant. RBIAS Pin To set the internal core bias current of the ADC, place a resistor (nominally equal to 10.0 k) to ground at the RBIAS pin. The resistor current is derived on-chip and sets the ADC's AVDD current to a nominal xxx mA at 50 MSPS. Therefore, it is imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance. Voltage Reference A stable and accurate 0.5 V voltage reference is built into the AD9271. This is gained up internally by a factor of 2, setting VREF to 1.0 V, which results in a full-scale differential input span of 2 V p-p for the ADC. The VREF is set internally by default; however, the VREF pin can be driven externally with a 1.0 V reference to achieve more accuracy. When applying the decoupling capacitors to the VREF, REFT, and REFB pins, use ceramic low ESR capacitors. These capacitors should be close to reference pins and on the same layer of the PCB as the AD9271. The recommended capacitor values and configurations for the AD9271 reference pin can be found in Figure 58. Rev. PrA | Page 33 of 58 AD9271 Table 13. Reference Settings Selected Mode External Reference Internal, 2 V p-p FSR SENSE Voltage AVDD AGND to 0.2 V Resulting VREF (V) N/A 1.0 Resulting Differential Span (V p-p) 2 x external reference 2.0 Preliminary Technical Data External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 61 shows the typical drift characteristics of the internal reference in 1 V mode. When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. The external reference is loaded with an equivalent 6 k load. An internal reference buffer generates the positive and negative full-scale references, REFT and REFB, for the ADC core. Therefore, the external reference must be limited to a nominal of 1.0 V. 5 Internal Reference Operation A comparator within the AD9271 detects the potential at the SENSE pin and configures the reference. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 58), setting VREF to 1 V. The REFT and REFB pins establish their input span of the ADC core from the reference configuration. The analog input fullscale range of the ADC equals twice the voltage at the reference pin for either an internal or an external reference configuration. VIN+ VIN- REFT ADC CORE 0.1F 0.1F REFB VREF 1F 0.1F SELECT LOGIC SENSE 0.5V 0.1F + 0 -5 Vref Error (%) -10 -15 -20 4.7F -25 0 0.5 1 1.5 Current Load (mA) 2 2.5 3 3.5 Figure 60. VREF Accuracy vs. Load, AD9271-50 0.02 0 -0.02 -0.04 06304-064 -0.06 VREF ERROR (%) -0.08 Figure 58. Internal Reference Configuration VIN+ VIN- REFT ADC CORE EXTERNAL REFERENCE VREF 1F* 0.1F* AVDD SENSE SELECT LOGIC 0.5V 0.1F 0.1F REFB 0.1F + -0.1 -0.12 -0.14 -0.16 -0.18 4.7F -0.2 -40 -20 0 20 TEMPERATURE (oC) 40 60 80 Figure 61. Typical VREF Drift, AD9271-50 *OPTIONAL. Figure 59. External Reference Operation Rev. PrA | Page 34 of 58 06304-065 Preliminary Technical Data SERIAL PORT INTERFACE (SPI) The AD9271 serial port interface allows the user to configure the signal chain for specific functions or operations through a structured register space provided inside the chip. This offers the user added flexibility and customization depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided down into fields, as documented in the Memory Map section. Detailed operational information can be found in the Analog Devices, Inc., user manual Interfacing to High Speed ADCs via SPI. There are three pins that define the serial port interface, or SPI, to this particular ADC. They are the SCLK, SDIO, and CSB pins. The SCLK (serial clock) is used to synchronize the read and write data presented to the ADC. The SDIO (serial data input/output) is a dual-purpose pin that allows data to be sent to and read from the internal ADC memory map registers. The CSB (chip select bar) is an active low control that enables or disables the read and write cycles (see Table 14). Table 14. Serial Port Pins Pin SCLK SDIO Function Serial Clock. The serial shift clock input. SCLK is used to synchronize serial interface reads and writes. Serial Data Input/Output. A dual-purpose pin. The typical role for this pin is as an input or output, depending on the instruction sent and the relative position in the timing frame. Chip Select Bar (Active Low). This control gates the read and write cycles. AD9271 In addition to the operation modes, the SPI port can be configured to operate in different manners. For applications that do not require a control port, the CSB line can be tied and held high. This places the remainder of the SPI pins in their secondary mode as defined in the Serial Port Interface (SPI) section. CSB can also be tied low to enable 2-wire mode. When CSB is tied low, SCLK and SDIO are the only pins required for communication. Although the device is synchronized during power-up, caution must be exercised when using this mode to ensure that the serial port remains synchronized with the CSB line. When operating in 2-wire mode, it is recommended to use a 1-, 2-, or 3-byte transfer exclusively. Without an active CSB line, streaming mode can be entered but not exited. In addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB- or LSB-first mode. MSB-first mode is the default at power-up and can be changed by adjusting the configuration register. For more information about this and other features, see the user manual Interfacing to High Speed ADCs via SPI. HARDWARE INTERFACE The pins described in Table 14 compose the physical interface between the user's programming device and the serial port of the AD9271. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. In cases where multiple SDIO pins share a common connection, care should be taken to ensure that proper VOH levels are met. Figure 62 shows the number of SDIO pins that can be connected together, assuming the same load as the AD9271 and the resulting VOH level. 1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715 CSB 0 10 20 30 40 50 60 70 80 90 100 NUMBER OF SDIO PINS CONNECTED TOGETHER Figure 62. SDIO Pin Loading Rev. PrA | Page 35 of 58 05967-037 The falling edge of the CSB in conjunction with the rising edge of the SCLK determines the start of the framing sequence. During an instruction phase, a 16-bit instruction is transmitted, followed by one or more data bytes, which is determined by Bit Fields W0 and W1. An example of the serial timing and its definitions can be found in Figure 63 and Table 15. In normal operation, CSB is used to signal to the device that SPI commands are to be received and processed. When CSB is brought low, the device processes SCLK and SDIO to process instructions. Normally, CSB remains low until the communication cycle is complete. However, if connected to a slow device, CSB can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. CSB can be stalled when transferring one, two, or three bytes of data. When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until the CSB is taken high to end the communication cycle. This allows complete memory transfers without having to provide additional instructions. Regardless of the mode, if CSB is taken high in the middle of any byte transfer, the SPI state machine is reset and the device waits for a new instruction. VOH AD9271 This interface is flexible enough to be controlled by either serial PROMS or PIC mirocontrollers. This provides the user an alternative method, other than a full SPI controller, to program the ADC (see the AN-812 Application Note). If the user chooses not to use the SPI interface, these pins serve a dual function and are associated with secondary functions Preliminary Technical Data when the CSB is strapped to AVDD during device power-up. See the section for details on which pin-strappable functions are supported on the SPI pins. tDS tS CSB tHI tDH tLO tCLK tH SCLK DON'T CARE DON'T CARE SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON'T CARE Figure 63. Serial Timing Details Table 15. Serial Timing Definitions Parameter tDS tDH tCLK tS tH tHI tLO tEN_SDIO tDIS_SDIO Minimum Timing (ns) 5 2 40 5 2 16 16 1 5 Description Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the clock Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 63). Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 63). Rev. PrA | Page 36 of 58 06304-068 Preliminary Technical Data MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: chip configuration register map (Address 0x00 to Address 0x02), device index and transfer register map (Address 0x05 and Address 0xFF), and program register map (Address 0x08 to Address 0x25). The left most column of the memory map indicates the register address number, and the default value is shown in the right most column. The (MSB) Bit 7 column is the start of the default hexadecimal value given. For example, Address 0x09, clock, has a default value of 0x01, meaning that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. This setting is the default for the duty cycle stabilizer in the on condition. By writing a 0 to Bit 6 of this address followed by an 0x01 in Register 0xFF (transfer bit), the duty cycle stabilizer turns off. It is important to follow each writing sequence with a transfer bit to update the SPI registers. For more information on AD9271 this and other functions, consult the user manual Interfacing to High Speed ADCs via SPI. RESERVED LOCATIONS Undefined memory locations should not be written to except when writing the default values suggested in this data sheet. Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. DEFAULT VALUES After a reset, critical registers are automatically loaded with default values. These values are indicated in Table 16, where an X refers to an undefined feature. LOGIC LEVELS An explanation of various registers follows: "Bit is set" is synonymous with "bit is set to Logic 1" or "writing Logic 1 for the bit." Similarly, "clear a bit" is synonymous with "bit is set to Logic 0" or "writing Logic 0 for the bit." Rev. PrA | Page 37 of 58 AD9271 Table 16. Memory Map Register Addr. Bit 7 (Hex) Parameter Name (MSB) Chip Configuration Registers 00 chip_port_config 0 Bit 6 LSB first 1 = on 0 = off (default) Bit 5 Soft reset 1 = on 0 = off (default) Bit 4 1 Bit 3 1 Bit 2 Soft reset 1 = on 0 = off (default) Preliminary Technical Data Default Value (Hex) 0x18 Bit 1 LSB first 1 = on 0 = off (default) Bit 0 (LSB) 0 Default Notes/ Comments The nibbles should be mirrored so that LSB- or MSB-first mode registers correctly regardless of shift mode. Default is unique chip ID, different for each device. This is a read-only register. Child ID used to differentiate graded devices. 01 chip_id Chip ID Bits 7:0 (AD9271 = 0x13), (default) Read only 02 chip_grade X X Child ID 6:4 (identify device variants of Chip ID) 00 = 50 MSPS (default) 01 = 40 MSPS 11 = 25 MSPS X X X X X X 0x00 Device Index and Transfer Registers 04 device_index_2 X X 05 device_index_1 X X FF device_update X X Clock Channel DCO 1 = on 0 = off (default) X Clock Channel FCO 1 = on 0 = off (default) X Data Channel H 1 = on (default) 0 = off Data Channel D 1 = on (default) 0 = off X Data Channel G 1 = on (default) 0 = off Data Channel C 1 = on (default) 0 = off X Data Channel F 1 = on (default) 0 = off Data Channel B 1 = on (default) 0 = off X Data Channel E 1 = on (default) 0 = off Data Channel A 1 = on (default) 0 = off SW transfer 1 = on 0 = off (default) 0x0F Bits are set to determine which on-chip device receives the next write command. Bits are set to determine which on-chip device receives the next write command. Synchronously transfers data from the master shift register to the slave. Determines various generic modes of chip operation. 0x0F 0x00 ADC Functions 08 modes X X X X 09 clock X X X X 0D test_io User test mode 00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once Reset PN long gen 1 = on 0 = off (default) Reset PN short gen 1 = on 0 = off (default) Internal power-down mode 000 = chip run (default) 001 = full power-down 010 = standby 011 = reset 100 = CW mode (TGC PWDN) X X X Duty cycle stabilizer 1 = on (default) 0 = off Output test mode--see Table 12 in the Digital Outputs and Timing section 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = -FS short 0100 = checkerboard output 0101 = PN 23 sequence 0110 = PN 9 0111 = one/zero word toggle 1000 = user input 1001 = one/zero bit toggle LNA bypass 1 = on 0 = off (default) 0x00 0x01 Turns the internal duty cycle stabilizer on and off. 0x00 When set, the test data is placed on the output pins in place of normal data. (Local, expect for PN sequence) Rev. PrA | Page 38 of 58 Preliminary Technical Data Addr. (Hex) Parameter Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 1010 = 1x sync 1011 = one bit high 1100 = mixed bit frequency (format determined by output_mode) X X X X Bit 0 (LSB) Default Value (Hex) AD9271 Default Notes/ Comments 0F Flex_channel_input 10 Flex_offset Filter cutoff frequency control 0000 = 0.7 x 1/3 x fSAMPLE 0001 = 0.8 x 1/3 x fSAMPLE 0010 = 0.9 x 1/3 x fSAMPLE 0011 = 1.0 x 1/3 x fSAMPLE 0100 = 1.1 x 1/3 x fSAMPLE 0101 = 1.2 x 1/3 x fSAMPLE 0110 = 1.3 x 1/3 x fSAMPLE X X 6-bit LNA offset adjustment Table = TBD X X X X X 0x30 Antialiasing filter cutoff (global) 0x20 11 Flex_gain X 14 output_mode X 15 output_adjust X 0 = LVDS ANSI (default) 1 = LVDS low power, (IEEE 1596.3 similar) X X X X Output invert 1 = on 0 = off (default) LNA gain 00 = 5x 01 = 6x 10 = 8x 00 = offset binary (default) 01 = twos complement 0x01 LNA force offset correction (local) LNA gain adjustment (global) Configures the outputs and the format of the data. 0x00 Output driver termination 00 = none (default) 01 = 200 10 = 100 11 = 100 X X X DCO and FCO 2x drive strength 1 = on 0 = off (default) 0x00 16 output_phase X X X X 19 user_patt1_lsb B7 B6 B5 B4 0011 = output clock phase adjust (0000 through 1010) (Default: 180 relative to DATA edge) 0000 = 0 relative to DATA edge 0001 = 60 relative to DATA edge 0010 = 120 relative to DATA edge 0011 = 180 relative to DATA edge 0100 = 240 relative to DATA edge 0101 = 300 relative to DATA edge 0110 = 360 relative to DATA edge 0111 = 420 relative to DATA edge 1000 = 480 relative to DATA edge 1001 = 540 relative to DATA edge 1010 = 600 relative to DATA edge 1011 to 1111 = 660 relative to DATA edge B3 B2 B1 B0 0x03 Determines LVDS or other output properties. Primarily functions to set the LVDS span and common-mode levels in place of an external resistor. On devices that utilize global clock divide, determines which phase of the divider output is used to supply the output clock. Internal latching is unaffected. 0x00 1A user_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 1B user_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 1C user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 1 LSB (global). User-defined pattern, 1 MSB (global). User-defined pattern, 2 LSB. (global) User-defined pattern, 2 MSB (global). Rev. PrA | Page 39 of 58 AD9271 Addr. (Hex) 21 Parameter Name serial_control Bit 7 (MSB) LSB first 1 = on 0 = off (default) Bit 6 X Bit 5 X Bit 4 X Bit 3 <10 MSPS, low encode rate mode 1 = on 0 = off (default) X Preliminary Technical Data Bit 0 (LSB) Bit 2 Bit 1 000 = 12 bits (default, normal bit stream) 001 = 8 bits 010 = 10 bits 011 = 12 bits 100 = 14 bits Default Value (Hex) 0x00 Default Notes/ Comments Serial stream control. Default causes MSB first and the native bit stream (global). 22 serial_ch_stat X X X X X 2B Flex_filter X Enable automatic low-pass tuning 1 = on 0 = off (default) X X X X X Channel Channel poweroutput down reset 1 = on 1 = on 0 = off 0 = off (default) (default) High-pass filter cutoff 00 = dc (default) 01 = 700 kHz 10 = 350 kHz 0x00 Used to power down individual sections of a converter (local). 0x00 Filter cutoff (global) 2C Analog_Input X X X X X X LOSW 1 = on 0 = off (default) 0x00 LNA active termination/input impedance (global) Crosspoint switch enable (local) 2D Cross_point_Switch X X X Crosspoint switch enable 0 0000 = CDW0p/n 0 0001 = CDW1p/n 0 0010 = CDW2p/n 0 0011 = CDW3p/n 0 0100 = CDW4p/n 0 0101 = CDW5p/n 0 0111 = power down CW channel 1 0000 = CDW0p SE 1 0001 = CDW1p SE 1 0010 = CDW2p SE 1 0011 = CDW3p SE 1 0100 = CDW4p SE 1 0101 = CDW5p SE 1 0111 = power down CW channel 1 1000 = CDW0n SE 1 1001 = CDW1n SE 1 1010 = CDW2n SE 1 1011 = CDW3n SE 1 1100 = CDW4n SE 1 1101 = CDW5n SE 1 1111 = power down CW channel 0x07 Rev. PrA | Page 40 of 58 Preliminary Technical Data Power and Ground Recommendations When connecting power to the AD9271, it is recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). The AD9271 also requires a 3.3 V supply (CWVDD) as well for the crosspoint section. If only one 1.8 V supply is available, it should be routed to the AVDD first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the DRVDD. The user should employ several decoupling capacitors on all supplies to cover both high and low frequencies. These should be located close to the point of entry at the PC board level and close to the parts with minimal trace lengths. A single PC board ground plane should be sufficient when using the AD9271. With proper decoupling and smart partitioning of the PC board's analog, digital, and clock sections, optimum performance is easily achieved. AD9271 exposed continuous copper plane on the PCB should mate to the AD9271 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be solder filled or plugged. To maximize the coverage and adhesion between the ADC and PCB, partition the continuous copper plane by overlaying a silkscreen on the PCB into several uniform sections. This provides several tie points between the two during the reflow process. Using one continuous plane with no partitions only guarantees one tie point between the AD9271 and PCB. See Figure 64 for a PCB layout example. For more detailed information on packaging and the PCB layout, see the AN-772 Application Note. SILKSCREEN PARTITION PIN 1 INDICATOR Exposed Paddle Thermal Heat Slug Recommendations It is required that the exposed paddle on the underside of the ADC is connected to analog ground (AGND) to achieve the best electrical and thermal performance of the AD9271. An 06304-069 Figure 64. Typical PCB Layout Rev. PrA | Page 41 of 58 AD9271 EVALUATION BOARD The AD9271 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configurations. The LNA is driven differentially through a transformer. Figure 65 shows the typical bench characterization setup used to evaluate the ac performance of the AD9271. It is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the signal chain. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance. See Figure x to Figure x for the complete schematics and layout diagrams that demonstrate the routing and grounding techniques that should be applied at the system level. Preliminary Technical Data is needed in addition to the other supplies. The 3.3 V supply, or AVDD_3.3 V, should have a 1 A current capability. To bias the crosspoint switch circuitry or CW section, separate +5 V and -5 V supplies are required. These should have 1 A current capability each. This section cannot be biased from a 6 V, 2 A wall supply. Separate supplies are required. INPUT SIGNALS When connecting the clock and analog source, use clean signal generators with low phase noise, such as Rohde & Schwarz SMHU or HP8644 signal generators or the equivalent. Use a 1 m, shielded, RG-58, 50 coaxial cable for making connections to the evaluation board. Enter the desired frequency and amplitude from the specifications tables. The evaluation board is set up to be clocked from the crystal oscillator, OSC401. If a different or external clock source is desired, follow the instructions for CLOCK outlined in the Default Operation and Jumper Selection Settings section. Typically, most Analog Devices evaluation boards can accept ~2.8 V p-p or 13 dBm sine wave input for the clock. When connecting the analog input source, it is recommended to use a multipole, narrow-band, band-pass filter with 50 terminations. Analog Devices uses TTE and K&L Microwave, Inc., band-pass filters. The filter should be connected directly to the evaluation board. POWER SUPPLIES This evaluation board comes with a wall-mountable switching power supply that provides a 6 V, 2 A maximum output. Simply connect the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter jack that connects to the PCB at P701. Once on the PC board, the 6 V supply is fused and conditioned before connecting to three low dropout linear regulators that supply the proper bias to each of the various sections on the board. When operating the evaluation board in a nondefault condition, L702 to L704 can be removed to disconnect the switching power supply. This enables the user to bias each section of the board individually. Use P501 to connect a different supply for each section. At least one 1.8 V supply is needed with a 1 A current capability for AVDD_DUT and DRVDD_DUT; however, it is recommended that separate supplies be used for both analog and digital domains. To operate the evaluation board using the SPI and alternate clock options, a separate 3.3 V analog supply OUTPUT SIGNALS The default setup uses the HSC-ADC-FPGA-8 high speed deserialization board to deserialize the digital output data and convert it to parallel CMOS. These two channels interface directly with the Analog Devices standard dual-channel FIFO data capture board (HSC-ADC-EVALB-DC). Two of the eight channels can then be evaluated at the same time. For more information on channel settings on these boards and their optional settings, visit www.analog.com/FIFO. WALL OUTLET 100V TO 240V AC 47Hz TO 63Hz 6V DC 2A MAX SWITCHING POWER SUPPLY - 3.3V + - + - 1.5V + - 3.3V + 1.8V + 1.8V - + - 3.3V 1.5V_FPGA GND GND GND GND GND DRVDD_DUT AVDD_3.3V AVDD_DUT 3.3V_D GND VCC ANALOG INPUT ROHDE & SCHWARZ, SMHU, 2V p-p SIGNAL SYNTHESIZER ROHDE & SCHWARZ, FS5A20 SPECTRUM ANALYZER BAND-PASS FILTER AD9271 VFAC3 OSCILLATOR CLK CW OUTPUT EVALUATION BOARD SPI SPI SPI Figure 65. Evaluation Board Connection Rev. PrA | Page 42 of 58 06304-070 CHA TO CHH 12-BIT SERIAL LVDS HSC-ADC-FPGA-8 HIGH SPEED DESERIALIZATION BOARD 2 CH 12-BIT PARALLEL CMOS SPI HSC-ADC-EVALB-DC FIFO DATA CAPTURE BOARD USB CONNECTION PC RUNNING ADC ANALYZER AND SPI USER SOFTWARE Preliminary Technical Data DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9271 Rev. A evaluation board. * POWER: Connect the switching power supply that is supplied in the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P701. AIN: The evaluation board is set up for a transformercoupled analog input with optimum 50 impedance matching out to 18 MHz (see Figure 66). For a different bandwidth response, change the 22 pF capacitor at the LNA (LI-x) analog input. AD9271 The evaluation board is already set up to be clocked from the crystal oscillator, OSC401. This oscillator is a low phase noise oscillator from Valpey Fisher (VFAC3-BHL-50MHz). If a different clock source is desired, remove R403, set Jumper J401 to disable the oscillator from running, and connect the external clock source to the SMA connector, P401. A differential LVPECL clock driver can also be used to clock the ADC input using the AD9515 (U401). Populate R406 and R407 with 0 resistors and remove R415 and R416 to disconnect the default clock path inputs. In addition, populate C405 and C406 with a 0.1 F capacitor and remove C409 and C410 to disconnect the default cloth path outputs. The AD9515 has many pin-strappable options that are set to a default mode of operation. Consult the AD9515 data sheet for more information about these and other options. * * * PDWN: To enable the power-down feature, short P303 to the on position (AVDD) on the PDWN pin. STDBY: To enable the standby feature, simply short P302 to the on position (AVDD) on the STDBY pin. GAIN: To change the gain on the VGA, drive these pins from 0 V to 1 V on J301. This changes the VGA gain from 0 dB to 30 dB. This feature can also be driven from the R335 and R336 on-board resistive dividers by installing a 0 resistor in R337. Non-SPI Mode: For users who wish to operate the DUT without using SPI, remove the jumpers on J501. This disconnects the CSB, SCLK, and SDIO pins from the control bus, allowing the DUT to operate in its simplest mode. Each of these pins has internal termination and will float to its respective level. Note that the device will only work in its default condition. CWD+,CWD-: To view muiltple CW outputs, jumper together the appropriate outputs on P403 and P404. All outputs are summed together on IOP and ION buses, fed to a 1:4 impedance ratio transformer, and buffered so that the user can view the output on a spectrum analyzer. This can be configured to be viewed in single-ended mode (default) or in differential mode. To set the voltage for the appropriate number of channels to be summed, change the value of R447 and R448 on the primary transformer (T402). D+, D-: If an alternative data capture method to the setup described in Figure 67 is used, optional receiver terminations, R318, R320 to R330, can be installed next to the high speed backplane connector. * Figure 66. Evaluation Board Full Power Bandwidth * * VREF: VREF is set to 1.0 V by tying the SENSE pin to ground, R317. This causes the ADC to operate in 2.0 V p-p full-scale range. A separate external reference option using the ADR510 or ADR520 is also included on the evaluation board. Populate R311 and R315 with 0 resistors and remove C307. Proper use of the VREF options is noted in the Voltage Reference section. RBIAS: RBIAS has a default setting of 10 k (R301) to ground and is used to set the ADC core bias current. To further lower the core power (excluding the LVDS driver supply), change the resistor setting. However, performance of the ADC may degrade depending on the resistor chosen. See RBIAS section for more information. CLOCK: The default clock input circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T401) that adds a very low amount of jitter to the clock path. The clock input is 50 terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs. * * * * Rev. PrA | Page 43 of 58 AD9271 R10 7 LO- A C10 3 R10 8 200 J103 R10 3 ADT1-1W T 1 R15 6 CTC 5 0-DN P 2 R16 0 50 4 0.1UF C10 9 0-DN P R11 9 50-DN P CT C GNDC 3 T10 3 R12 5 LO- C C11 1 LOSW A 0.1UF C12 3 LI C LIA 1K-DN P R12 6 200 LOSW C 1K-DN P J101 R10 2 0 CT A 5 0-DN P C10 1 LGA 6 0.1UF R13 0 0 R13 9 0-DN P R14 5 10K-DN P R15 2 0 R14 1 10K-DN P C10 2 22P F C10 4 0.1UF-DN P AVDD_DU T 3 T10 1 0.1UF ADT1-1W T 1 R15 CT A 4 2 6 R15 8 50 0.1UF 4 C12 1 AIN CHA R10 1 50-DN P GND A AVDD_DU T R14 9 0-DN P AIN CHC LGC 0.1UF C11 0 22P F C11 2 0.1UF-DN P 1 R10 6 0 R11 3 0-DN P R12 1 0-DN P C11 9 0.1UF-DN P R10 9 0-DN P R15 0 0-DN P C11 7 0.1UF-DN P R13 7 0-DN P R14 2 10K-DN P 1 R14 6 10K-DN P R12 4 0 R12 7 0-DN P R11 6 LO- B C10 7 R11 7 200 LOSW B 0.1UF J104 LIB R15 5 CTB R15 9 50 C10 5 LGB 0.1UF C10 6 22P F C10 8 0.1UF-DN P R14 0 0-DN P AVDD_DU T R15 3 0 R14 7 10K-DN P 5 0-DN P 3 T10 2 R13 4 LO- D C11 5 1K-DN P R13 5 200 R12 9 0-DN P R12 8 50-DN P CTD GND D ADT1-1W T 1 5 3 4 R15 7 2 6 T10 4 06304-086 Figure 67. Evaluation Board Schematic, DUT Analog Inputs 1K-DN P Rev. PrA | Page 44 of 58 0.1UF J102 R11 1 ADT1-1W T 1 0.1UF 2 6 4 0-DN P R11 0 50-DN P CT B GNDB C12 2 LOSW D C12 4 LID CTD 0-DN P R16 1 50 0.1UF C11 3 LGD 0.1UF C11 4 22P F C11 6 0.1UF-DN P AIN CHB AVDD_DU T R13 8 0-DN P R14 3 10K-DN P R15 1 0 AIN CHD 1 R11 5 0 R11 8 0-DN P R10 4 0-DN P R11 2 0-DN P C11 8 0.1UF-DN P R14 4 10K-DN P 1 R12 2 0-DN P R13 1 0-DN P C12 0 0.1UF-DN P R14 8 10K-DN P R13 3 0 Preliminary Technical Data R13 6 0-DN P R20 7 LO- E C20 3 R20 8 200 J203 R21 3 3 6 2 CTG 0-DN P GNDG ADT1-1W T C20 2 22P F C20 4 0.1UF-DN P R23 9 0-DN P AVDD_DU T R25 1 0 R24 5 10K-DN P 1 4 0.1UF C21 0 22P F R25 6 0.1UF R26 0 50 C20 9 5 T203 R22 5 LO- G C21 1 LOSW E 0.1UF C22 3 LIG LIE 1K-DN P R22 6 200 LOSW G 1K-DN P J201 R20 2 3 6 2 0-DN P C20 1 LGE 0.1UF GNDE ADT1-1W T AVDD_DU T R24 9 0 R24 2 10K-DN P 1 4 R25 8 50 CTG R25 4 CTE 0.1UF R21 9 50-DN P 5 T201 0.1UF C22 1 Preliminary Technical Data AIN CHE 0-DN P R20 1 50-DN P CTE 0-DN P AIN CHG LGG R20 3 0-DN P C21 2 0.1UF-DN P 1 R20 6 0 R23 1 0-DN P R23 7 0-DN P C21 9 0.1UF-DN P R20 9 0-DN P R21 2 0-DN P R22 1 0-DN P C21 7 0.1UF-DN P R24 3 10K-DN P 1 R24 6 10K-DN P R22 4 0 R22 7 0-DN P R21 6 LO- F C20 7 R21 7 200 LOSW F 0.1UF J204 LIF R25 5 CTF R25 9 50 C20 5 LGF 0.1UF C20 6 22P F C20 8 0.1UF-DN P R24 0 0-DN P GND H 1 ADT1-1W T AVDD_DU T R25 2 0 R24 7 10K-DN P 4 0.1UF C21 4 22P F C21 6 0-DN P 1 ADT1-1W T AVDD_DU T R25 0 0 R20 4 10K-DN P 4 0.1UF R22 9 0-DN P R22 8 50-DN P CTH 5 2 C22 4 3 T204 R23 4 LO- H C21 5 1K-DN P R23 5 200 6 LOSW H 06304-087 Figure 68. Evaluation Board Schematic, DUT Analog Inputs (Continued) 1K-DN P Rev. PrA | Page 45 of 58 0.1UF J202 R21 1 3 6 2 5 T202 C22 2 0-DN P R21 0 50-DN P CTF GND F LIH AIN CHF AIN CHH R25 7 0-DN P CTH R26 1 50 0.1UF C21 3 LGH R23 8 0-DN P 0.1UF-DN P 1 R21 5 0 R21 8 0-DN P R22 2 0-DN P R23 0 0-DN P C21 8 0.1UF-DN P R24 4 10K-DN P 1 R24 1 0-DN P R25 3 0-DN P C22 0 0.1UF-DN P R24 8 10K-DN P R23 3 0 R23 6 0-DN P AD9271 AD9271 GAIN DRIVE INPUT AVDD_DU T IN J301 Referenc e Decoupling CW 0.1U F 10K AVDD_DUT LOSW E LO- E CWD5+ CWD5 - CWD4+ CWD4 - CWD3+ CWD3 - AVDD_3.3 V CWD2+ CWD2 - CWD1+ CWD1 - CWD0+ CWD0 - LO-D LOSW D VREF_DU T VSENSE_DU T R30 1 C303 0.1U F R30 3 C304 0.1U F R33 5 8K 10 0 R30 2 R33 7 50 C302 4.7UF C309 GGND 0.1UF P3 0 1 GNDC D1 60 0 C308 0.1UF 0-DN P R205-R21 Opti on al Digital Outputs 0 Ou t pu t Termi n ati on s R30 5 R336 10K DC O C1 0 40 GN D DC 59 9 D1 0 50 C30 1 AVDD_DU T 0-DN P FC O C9 39 GN D DC 58 8 R304 100-DNP R331 100-DNP DC O R318 100-DNP D9 49 FC O R320 100-DNP D 84 8 CH A C 38 8 57 C7 37 CH A GN D DC 7 R321 100-DNP D7 GN D DC 6 47 CH B CH B 56 C6 D6 U301 CH C R322 100-DNP 36 55 C5 GN D DC 5 46 D5 CH C 92 91 88 10 1 10 0 99 98 97 96 95 94 93 90 89 87 86 85 84 83 82 81 80 79 78 77 76 CH D 35 54 C 34 4 GN D DC 4 45 D 44 4 GN D DC 53 3 CH D R323 100-DNP CHE PAD LO-E REF T REFB VREF RBIA S CWD5 - CWD4 - CWD3 - SENS E CWD2 - CWD1 - LOSW E RAVD D GAIN + CWD0 - LOSW D 1 LID 74 LGD 73 72 71 LO- C LOSW C LIC LGC 70 69 68 67 66 65 LO-B LOSW B LIB LGB 64 63 62 61 60 59 LO-A LOSW A LIA LGA R33 8 10 K GAIN - LO-D CHE 75 LID CHF CHG CHH CWD5+ CWD4+ CWD3+ CWVDD CWD2+ CWD1+ LIE LGD AVDD D AVDD_CH D AVDD D LO- C LOSW C LIC LGC AVDD C AVDD_CHC AVDD C LO-B LOSW B LIB LGB AVDD B AVDD_CHB AVDD_DU T AVDD B LO-A LOSW A LIA LGA AVDD A AVDD A CSB SDIO 55 54 53 52 SCL K 51 R31 9 1K LIE CWD0+ C3 33 GN D DC 52 C2 32 GN D DC 51 C1 31 GNDA B1 30 A1 0 10 GNDA 9 B 29 A9 9 GNDA 8 B 28 A8 8 GNDA 7 B 27 A7 7 GNDA 6 B 26 A6 6 GNDA 5 B 25 0 1 2 D3 43 CHF D2 42 LGE 2 LGE CHG D1 41 3 AVDD E AVDD_CH E CHH B1 0 20 4 AVDD E R324 100-DNP R327 100-DNP R328 100-DNP R329 100-DNP R330 100-DNP B9 LO- F 5 LO- F 19 6 LOSW F LOSW F B8 18 7 LIF LIF B7 17 8 LGF LGF B6 16 9 AVDDF SCLK_CH B AVDD_CHF 5 SDI_ CH B A5 GNDA 4 B 24 A4 4 GNDA 3 B 23 A3 3 B 51 5 SCLK_CH A B4 14 10 AVDDF SDI_CHA CSB3 _ CH B B3 GNDA 2 B 22 13 LO-G 11 LO-G CSB1_CH A CSB4 _ CH B A2 2 GNDA 1 B 21 B2 12 LOSW G 12 LOSW G AD9271 CSB2_CH A SD O_ CH B A 11 B 11 1 LIG 13 LIG SDO_CH A LGG 14 LGG DRVD D D-H D+H D-G D+G D-F D+F D-E D+E DCO - DCO + FCO- FCO+ D-D D+D D-C D+ C D-B D+ B D-A D+ A DRVD D STDBY PWDN 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CH H CH H CHG CHG CH F CH F CHE CHE CH A DC O DC O FCO FCO CHD CHD CH C CH C CH B CH B CH A DRVDD_DU T AVDD_DUT DRVDD_DU T 06304-088 AVDD_DU T Figure 69. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface NC DVDD Rev. PrA | Page 46 of 58 58 57 56 AVDD_DU T 15 AVDD G AVDD_CH G 16 AVDD G LO- H 17 LO- H LOSW H 18 LOSW H LIH 19 OPTIONAL EXT REF U30 2 0 TRIM/NC LIH R30 9 1K ReferenceCircuitry R31 1 0-DN P AD R510_2 1V VOU T R31 2 VREF_DU T VSENSE_DU Vref Sel ec t R31 5 DN P T LGH 20 LGH 21 AVDDH G ND AVDD_DU AVDD_CH H 22 AVDD_CHA DN P Vref = E xt ern a l AVDDH T R31 6 CLK 23 CLK - CSB_DUT SDIO_DU T SCLK_DU T C30 5 R30 8 470K-DN P 0.1UF C30 6 0.1UF C30 7 1U F CLK 24 R310 10K-DN P DN P Vref=0.5V(1+R313/R312 ) CW CLK + R31 3 DN P AVDD_DU T 25 CVDD R31 7 0 Vref=1 V Remove u s in g C3 0 7 ext ern al wh e n Vre f P302 1 2 BERG69157-10 2 R32 5 1K R32 6 1K 1 2 BERG69157-10 2 Preliminary Technical Data P303 J402 J403 CW DOPPLER CIRCUITRY R45 9 0-DN P R45 5 50 50 R45 8 R46 1 0-DN P AOUT IOP ION CWD2 R46 4 0-DN P R46 3 0-DN P AOUT CWD1 R46 0 0-DN P R46 2 0-DN P P40 4 P40 3 1 CWD5 CWD5+ 1 2 2 3 CWD4 - C419 0.1UF C420 0.1UF +5V CWD4+ 3 4 4 5 CWD3 - R45 3 IOP 75 0 R45 4 R45 1 75 0 CWD3+ T402 3 CWD2+ C422 0.1UF 5 6 7 8 CWD2 - 6 7 8 9 Preliminary Technical Data 1 R44 7 12 5 4 0 -5V AD812A R CWD1+ R44 6 AVDD_3.3V 5 2 9 10 CWD1 - 0 R45 2 10 11 R44 8 12 5 6 CWD0+ 0 1 ADTT41 11 12 CWD0 - ION R46 5 0 0 R45 0 12 C421 0.1UF R425 AVDD_3.3V R424 DNP S0 0 0 CWD1 R44 9 0-DN P R46 6 0-DN P CWD2 AD9515 Pin-strap setting s AVDD_3.3V S1 R426 DNP 0 R427 0 AVDD_3.3V S6 AVDD_3.3V S2 R428 DNP 0 R429 0 AVDD_3.3V S7 R430 AVDD_3.3V S3 DNP R432 AVDD_3.3V S4 DNP R434 0 0 R431 0 AVDD_3.3V S8 R433 0 AVDD_3.3V S9 R435 R438 DNP R440 DNP R442 DNP R444 0 0 0 R439 0 R436 0 R437 DNP 0 AVDD _3.3 V C401 0.1UF 3 DISABLEOSC201 Optional Clock Oscillator AVDD_3.3V ENABLEOSC20 1 12 VCC OUT GND OPT_CLK R406 U401 5 R40 2 10 K R40 8 DN P R41 0 10 K C40 5 R40 9 DN P R40 1 10 K AVDD_3.3V OPTIONAL CLOCK DRIVE CIRCUIT R441 0 32 1 31 33 RSET GND 0-DNP 2 R41 1 50-DN P VS VREF S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 6 7 8 9 10 11 12 13 14 15 16 06304-089 CLK 0.1UF C409 Figure 70. Evaluation Board Schematic, Clock and CW Doppler Circuitry R40 4 50 25 Enc OPT_CLK R41 5 3 T401 6 S0 Rev. PrA | Page 47 of 58 OE 3 R41 4 4.12 K R443 0 AVDD_3.3V 10 R445 AVDD_3.3V CLK 0.1UF-DN P DNP 23 R42 2 10 0 0 0 AVDD_3.3V S5 S10 DNP 0 0 CLK CLKB GND_PA D OUT0 OUT0 B LVPECLOUTPU T C40 6 3 AD9515 SIGNAL=AVDD_3.3V;4,17,20,21,24,26,29,3 0 SIGNAL=DNC;27,2 8 22 0.1UF-DN P CLK R42 0 24 0 R42 1 24 0 Encod e R40 3 0 OPT_CLK 0-DNP SYNCB R41 2 R41 3 10 K DN P R407 5 AVDD_3.3V OUT1 OUT1 B 19 18 Inpu t P401 C40 7 0.1UF-DN P R42 3 10 0 C40 8 1 S10 S9 S8 5 2 LVDSOUTPU T S7 S6 S5 S4 S3 S2 S1 S0 C412 0.1UF C413 0.1UF C414 0.1UF C415 0.1UF C416 0.1UF C417 0.1UF C418 0.1UF Clock Circuit C40 2 0.1UF 0 C410 0.1UF CLK 0.1UF-DN P DN P OPT_CLK R416 1 4 R418 0 P402 0 ADT1-1W T C411 0.1UF 0 R417 Enc R40 5 0 C40 3 0.1UF CLIPSINEOUT(DEFAULT ) AD9271 AD9271 SPI CIRCUITRY FROM FIFO Power Supply Inpu t 6V, 2A ma x L70 1 PWR_IN D702 D703 D704 D705 PWR_OUT 2A 2A 2A 2A CB 2 CG 4 CG 5 F701 1 BIAS P7 0 1 1 SMDC110F C704 3 PSG CG 6 CSB1_CHA SCLK_CHA SDI_CHA SDO_CHA GREEN CR702 D701 FLTHMURATABNX01 6 2 7.5V POWE R CON00 5 2.5MM JACK R71 6 24 0 3 10UF 2A AVDD_3.3V P50 2 AVDD_DUT R71 0 1K 1 AVDD_CH A 2 BERG69157-10 2 +/- 5V Power Inpu t P51 1 L50 1 10U H +5 V C50 1 10U F C50 2 0.1UF Optional Powe r Inpu t 3.3V_AVD D L70 3 10U H AVD D _3.3 V C70 9 10U F C71 0 0.1UF +3.3 V P50 3 SDIO_DU T 1 2 3 3 4 5 -5 V DUT_ DRVD D L70 2 10U H L50 2 10U H DUT_AVD D P50 1 1 2 1 AVDD_CH B 2 BERG69157-10 2 P50 4 R71 2 NC7WZ0 7 1K R71 3 1K AVDD_DUT WEILANDZ5.531.3325. 0 1 AVDD_CH C 1A1 Y1 6 2 BERG69157-10 2 AVDD_DU T +1.8 V 6 R71 1 10 K 2 GND AVDD_DUT C50 3 10U F C50 4 0.1UF 5 VCC Y2 4 P50 5 C70 7 10U F C70 8 0.1UF 3A2 U702 1 AVDD_CH D 2 BERG69157-10 2 C702 0.1UF P50 6 L70 4 10U H DRVDD_DU C71 1 10U F C71 2 0.1UF T +1.8 V 1 AVDD_CH E NC7WZ1 6 1A1 SCLK_DU T Y1 6 2 GND 5 VCC GN D Test Point s 2 BERG69157-10 2 P50 7 1 1 1 1 AVDD_DUT CSB_DU T C703 0.1UF 1 1 1 1 GND GND 1 1 06304-090 Preliminary Technical Data DNP: DO NOT POPULAT E 1 GND Figure 71. Evaluation Board Schematic, Power Supply Inputs and SPI Interface Circuitry 3A2 U703 R71 4 10 K R71 5 10 K Rev. PrA | Page 48 of 58 Y2 4 1 AVDD_CH F 2 BERG69157-10 2 P50 8 Decoupling Capacitor s AVDD_CH G AVDD_ CH H AVDD_ CH G AVDD_ CH F AVDD _ CH E AVD D_ CH D AVDD_ CH C 1 2 BERG69157-10 2 P50 9 C73 0 0.1UF C73 1 0.1UF C73 2 0.1UF C73 3 0.1UF C73 4 0.1UF C73 5 0.1UF 1 AVDD_CHH 2 BERG69157-10 2 U70 7 8 L70 5 10U H ADP33339AKC-3. 3 4 C71 5 C71 9 1U F 1U F 1U F C72 0 D UT_AVD D 4 PWR_ I N U70 5 ADP33339AKC-1. L70 7 10U H 3.3V_AVD D AVDD_ CH B AVDD _ CH A PWR_OU T 3 INPUT 2 OUTPUT 1 OUTPUT 4 3 INPUT 2 OUTPUT 1 OUTPUT 4 AVDD_DUT C71 4 1U F C74 4 0.1UF C74 5 0.1UF C74 6 0.1UF C74 7 0.1UF C74 8 0.1UF U70 4 8 L70 6 10U H 4 DUT_ DRVD D ADP33339AKC-1. AVDD_3.3V PWR_OU T 3 INPUT C71 7 1U F 2 OUTPUT 1 OUTPUT 4 DRVDD_DU T C74 2 C74 0 0.1UF C74 1 0.1UF C75 1 0.1UF 0.1UF C74 3 0.1UF C71 6 1U F Preliminary Technical Data AD9271 Figure 72. Evaluation Board Layout, Top Side 06304-081 Figure 73. Evaluation Board Layout, Ground Plane (Layer 2) Rev. PrA | Page 49 of 58 06304-082 AD9271 Preliminary Technical Data Figure 74. Evaluation Board Layout, Power Plane (Layer 3) Figure 75. Evaluation Board Layout, Power Plane (Layer4) Rev. PrA | Page 50 of 58 06304-084 06304-083 Preliminary Technical Data AD9271 Figure 76. Evaluation Board Layout, Ground Plane (Layer 5) Figure 77. Evaluation Board Layout, Bottom Side Rev. PrA | Page 51 of 58 06304-080 06304-085 AD9271 Table 17. Evaluation Board Bill of Materials (BOM)1 Qnty. per Board 1 71 Preliminary Technical Data Item 1 2 REFDES AD9271BSVZ_REVC C101, C103, C105, C107, C109, C111, C113, C115, C121 to C124, C201, C203, C205, C207, C209, C211, C213, C215, C221 to C224, C301, C303 to C306, C308 to C309, C401 to C403, C409 to C422, C502, C504, C702 to C703, C708, C710, C712, C730 to C735, C740 to C748, C751 C102, C106, C110, C114, C202, C206, C210, C214 C302 C307, C714 to C717, C719 to C720 C501, C503, C707, C709, C711 C704 Device PCB Capacitor Pkg. PCB C0402 Value PCB 0.1 F 10 V ceramic X5R 0402 Mfg. Panasonic Mfg. Part Number ECJ-0EB1A104K 3 8 Capacitor C0402 Ceramic 22 pF 5% 50 V NP0 0402 Ceramic 4.7 F 6.3 V X5R 0603 1 F 6.3 V ceramic X5R 0603 Ceramic 10 F 6.3 V X5R 0603 10 F, 6032-28, tantalum, 16 V, 10% tol Schottky GP LN 20 mA Green USS Type 0603 4 V, 5 m candela Rectifier SIL 2 A 50 V DO-214AA Polyswitch 1.10 A reset fuse SMD AVX 04025A220JAT2A 4 5 6 7 1 7 5 1 Capacitor Capacitor Capacitor Capacitor C0603 C0603 C0603 C6032 AVX Panasonic Panasonic Kemet C0603C475K9PACTU ECJ-1VB0J105K ECJ-1VB0J106M T491C106K016AS 8 9 1 1 CR401 CR702 Diode LED SOT23 LED0603 AVAGO (Agilent) Panasonic HSMS-2812-TR1G LNJ314G8TRA 10 11 12 5 1 13 D701 to 705 F701 J101 to J104, J201 to J204, J301, J402 to J403, P401 to P402 J401 Diode Fuse Connector SMBJ Micro Commercial Co. Tyco/Raychem Samtec/Johnson S2A-TP NANOSMDC110F-2 SMA-J-P-X-ST-EM1/ 142-0711-821 CNSAMTEC-SMA-J- CONN-PCB coax SMA end launch 13 1 Connector CNBERG1X3H205LD Header, 3-pin, male, single row, straight Header, 8-pin, male, double row, straight Samtec TSW-103-08-G-S 14 1 J501 Connector CNBERG2X4H350LD Samtec TSW-105-08-T-D Rev. PrA | Page 52 of 58 Preliminary Technical Data Item 15 16 Qnty. per Board 10 2 REFDES P302 to P303, P502 to P509 P403 to P404 Device Connector Connector Pkg. CNBERG69157-102 CNBERG2X6H330LD Value 100 mil header jumper, 2-pin 100 mil header, male, 2 x 6 double row straight Bead core 3.2 x 2.5 x 1.6 SMD 1210, 10 H Filter, BNX016-01, EMIFIL LC block OSC14P4_CB3 Crystal, dual footprint, see eng Header, right angle, 2-pair, 25 mm, header assembly 0.08", PCMT R0402 DC power, PC mount 0 1/16 W 5% 0402 SMD Mfg. Samtec Samtec AD9271 Mfg. Part Number TSW-102-07-G-S TSW-110-08-G-D/ TSW-106-08-G-D 17 8 L501 to L502, L702 to L707 L701 OSC401 P301 Ferrite Bead L1210 Panasonic EXC-CL3225U1 18 19 20 1 1 1 Choke coil Oscillator Connector Murata Valpey Fisher Tyco/AMP BNX016-01 VFAC3-BHL-50MHz 6469169-1 21 23 1 38 P701 R102, R103, R106, R111, R115, R124, R129, R130, R133, R151, R152, R153, R202, R206, R211, R213, R215, R224, R229, R233, R249 R252, R305, R317, R403, R405, R415 to R418, R446, R450 to R452, R465, R466 R108, R117, R126, R135, R208, R217, R226, R235 R158 to R161, R258 to R261, R302, R404, R455, R458 R301, R338, R401 to R402, R410, R413, R711, R714 to R715 R303, R422 to R423 R308 R309, R319, R325, R326, R710, R712, R713 R335 Connector Resistor Switchcraft Panasonic RAPC722X ERJ-2GE0R00X 24 8 Resistor R0402 200 1/16 W 0.5% 0402 SMD 49.9 1/16 W 0.5% 0402 SMD 10 k 1/16 W 5% 0402 SMD 100 1/16 W 1% 0402 SMD 470 k 1/16 W 5% 0402 SMD 1.00 k 1/16 W 1% 0402 SMD 8.06 k 1/16 W 1% 0402 SMD Yageo America RR0510P-201-D 25 12 Resistor R0402 Susumu Co. RR0510R-49R9-D 26 9 Resistor R0402 Panasonic ERJ-2GEJ103X 27 28 29 3 1 7 Resistor Resistor Resistor R0402 R0402 R0402 Panasonic Panasonic Panasonic ERJ-2RKF1000V RC0402JR-07470KL ERJ-2RKF1001X 30 1 Resistor R0402 Yageo RC0402FR-078K06L Rev. PrA | Page 53 of 58 AD9271 Item 31 32 33 34 Qnty. per Board 2 1 3 11 REFDES R310, R336 R414 R420 to R421, R716 R424, R427, R429, R431, R433, R435 to R436, R439, R441, R443, R445 R447 to R448 Device Potentiometer Resistor Resistor Resistor Pkg. 3-lead R0402 R0402 R0201 Value 10 k, one turn, SMT Preliminary Technical Data Mfg. Murata Panasonic Mfg. Part Number PVA2A103A01R00 ERJ-2RKF4121X 4.12 k 1/16 W 1% 0402 SMD Thick film, SMT 0402, 240 0.0 1/20 W 5% 0201 SMD Panasonic ERJ-1GE0R00C 35 2 Resistor R0402 124 1/16 W 0.1% 0402 SMD Susumu Co. RG10P124BCT-ND 36 37 38 39 40 2 9 1 1 1 R453 to R454 T101 to T104, T201 to T204, T401 T402 U301 U302 Resistor Transformer Transformer IC IC R0402 MINICD542 MINICKCD637 SV-100-3 SOT23 750 1/16 W 0.1% 0402 SMD XFMR RF ADTT4-1, CD542 Octal LNA/ VGA/AAF/ADC ADR510, 1.0 V precision low noise shunt V REF AD9515, CLK DIST, 32 LFCSP, 5 x 5 mm AD812AR, dual, current feedback op amp, SO8 NC7WZ07, dual buffer, SC88 NC7WZ16P6X, UHS dual buffer, SC88 Regulator, high accuracy, ADP3339AKC-1.8, 1.8 V Regulator, high accuracy, ADP3339AKC-3.3, 3.3 V Susumu Co. Mini Circuits Mini Circuits Analog Devices Analog Devices RG10P750BCT-ND ADT1-1WT ADTT4-1 AD9271BSVZ ADR510 41 1 U401 IC LFCSP32-5X5-LP Analog Devices AD9515 42 1 U402 IC SO8 Analog Devices AD812AR 43 44 1 1 U702 U703 IC IC SC88 SC88 Fairchild Fairchild NC7WZ07P6X_NL NC7WZ16P6X_NL 45 2 U704, U707 IC SOT223-2 Analog Devices ADP3339AKC-1-8 46 1 U705 IC SOT223-2 Analog Devices ADP3339AKC-3-3 Rev. PrA | Page 54 of 58 Preliminary Technical Data Item 47 Qnty. per Board 4 REFDES MP101 to MP104 Device Assembly Pkg. Insert into four large holes on corners of board from the bottom side Place into J502-509 Value CBSB-14-01, 7/8" height, standoffs for circuit board support, no adhesive SNT-100-BK-G-H, 100 mil jumpers Mfg. Richco AD9271 Mfg. Part Number CBSB-14-01 48 6 MP105 to MP108 Assembly Samtec SNT-100-BK-G-H 1 This BOM is RoHS compliant. Rev. PrA | Page 55 of 58 AD9271 OUTLINE DIMENSIONS 0.75 0.60 0.45 1.20 MAX 100 1 PIN 1 Preliminary Technical Data 16.00 BSC SQ 14.00 BSC SQ 76 75 76 75 100 1 TOP VIEW (PINS DOWN) EXPOSED PAD 9.50 SQ 1.05 1.00 0.95 0 MIN 0.15 0.05 SEATING PLANE 0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY 25 26 51 50 51 50 BOTTOM VIEW (PINS UP) 26 25 VIEW A 0.50 BSC LEAD PITCH 0.27 0.22 0.17 VIEW A ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD NOTES: THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS. Figure 78. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-100-3) Dimensions shown in millimeters ORDERING GUIDE Model AD9271BSVZ-501 AD9271BSVZRL7-501 AD9271BSVZ-401 AD9271BSVZRL7-401 AD9271BSVZ-251 AD9271BSVZRL7-251 AD9271-50EBZ1 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C 080706-A Package Description 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel Evaluation Board Package Option SV-100-3 SV-100-3 SV-100-3 SV-100-3 SV-100-3 SV-100-3 Z = Pb-free part. Rev. PrA | Page 56 of 58 Preliminary Technical Data NOTES AD9271 Rev. PrA | Page 57 of 58 AD9271 NOTES Preliminary Technical Data (c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06304-0-3/07(PrA) Rev. PrA | Page 58 of 58 |
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